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    DATA PROCESSING DEVICE
    1.
    发明公开
    DATA PROCESSING DEVICE 审中-公开
    数据处理设备

    公开(公告)号：EP2816466A1

    公开(公告)日：2014-12-24

    申请号：EP12868386.9

    申请日：2012-02-14

    申请人： Renesas Electronics Corporation

    发明人： ISHIZAKI, Masakatsu

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0884 ,  G06F12/0888 ,  G06F2212/1028 ,  G06F2212/452 ,  Y02D10/13

    摘要： A data processor of an embodiment includes a memory, an instruction cache, a processing unit (CPU), and a fetch process control unit. The memory stores a program in which a plurality of instructions are written. The instruction cache operates only when a branch instruction included in the program is executed, and data of a greater capacity than a width of a bus of the memory is read from the memory and stored in the instruction cache in advance. The processing unit accesses both the memory and the instruction cache and executes, in a pipelined manner, instructions read from the memory or the instruction cache. The fetch process control unit generates, in response to a branch instruction executed by the processing unit, a stop signal for stopping a fetch process of reading an instruction from the memory, and outputs the stop signal to the memory.

    摘要翻译： 实施例的数据处理器包括存储器，指令高速缓存，处理单元（CPU）和提取处理控制单元。 存储器存储写入了多个指令的程序。 指令高速缓冲存储器仅在程序中包含的分支指令被执行时才运行，并且从存储器中读取比存储器的总线宽度更大容量的数据并预先存储在指令高速缓冲存储器中。 处理单元访问存储器和指令高速缓存，并以流水线方式执行从存储器或指令高速缓存读取的指令。 提取处理控制单元响应于由处理单元执行的分支指令，生成用于停止从存储器读取指令的提取处理的停止信号，并且将停止信号输出到存储器。