公开(公告)号：EP2804316A2

公开(公告)日：2014-11-19

申请号：EP14164157.1

申请日：2014-04-10

申请人： Renesas Electronics Corporation

发明人： FUNATO, Yoshihiro ,  KUMAMOTO, Toshio ,  YOSHIZAWA, Tomoaki ,  KUROOKA, Kazuaki

IPC分类号： H03F3/393

CPC分类号： H03F3/2171 ,  H03F3/005 ,  H03F3/393 ,  H03F3/45179 ,  H03F3/45192 ,  H03F3/45762 ,  H03F3/45946 ,  H03F2200/264 ,  H03F2200/271 ,  H03F2200/375 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/81 ,  H03F2203/45012 ,  H03F2203/45028 ,  H03F2203/45116 ,  H03F2203/45136 ,  H03F2203/45138 ,  H03F2203/45174 ,  H03F2203/45212 ,  H03F2203/45512 ,  H03F2203/45528 ,  H03F2203/45558 ,  H03F2203/45594 ,  H03F2203/45601 ,  H03F2203/45604 ,  H03F2203/45631 ,  H03F2203/45632 ,  H03F2203/45634 ,  H03F2203/45641 ,  H03F2203/45681 ,  H03F2203/45698 ,  H03F2203/45726

摘要： A signal processing circuit includes a chopper amplifier (1) that has a differential amplifier circuit (AMP1) that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit (1B) that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier (1) generates. Differential signals inputted into the differential amplifier circuit (AMP1) are interchanged for every first phase period and second phase period, and the adder circuit (1B) generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.

公开(公告)号：EP2804316A3

公开(公告)日：2015-09-16

申请号：EP14164157.1

申请日：2014-04-10

申请人： Renesas Electronics Corporation

发明人： FUNATO, Yoshihiro ,  KUMAMOTO, Toshio ,  YOSHIZAWA, Tomoaki ,  KUROOKA, Kazuaki

IPC分类号： H03F3/393 ,  H03F3/00 ,  H03F3/45

CPC分类号： H03F3/2171 ,  H03F3/005 ,  H03F3/393 ,  H03F3/45179 ,  H03F3/45192 ,  H03F3/45762 ,  H03F3/45946 ,  H03F2200/264 ,  H03F2200/271 ,  H03F2200/375 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/81 ,  H03F2203/45012 ,  H03F2203/45028 ,  H03F2203/45116 ,  H03F2203/45136 ,  H03F2203/45138 ,  H03F2203/45174 ,  H03F2203/45212 ,  H03F2203/45512 ,  H03F2203/45528 ,  H03F2203/45558 ,  H03F2203/45594 ,  H03F2203/45601 ,  H03F2203/45604 ,  H03F2203/45631 ,  H03F2203/45632 ,  H03F2203/45634 ,  H03F2203/45641 ,  H03F2203/45681 ,  H03F2203/45698 ,  H03F2203/45726

摘要： A signal processing circuit includes a chopper amplifier (1) that has a differential amplifier circuit (AMP1) that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit (1B) that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier (1) generates. Differential signals inputted into the differential amplifier circuit (AMP1) are interchanged for every first phase period and second phase period, and the adder circuit (1B) generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.

摘要翻译： 一种信号处理电路，包括斩波器放大器（1）也有一个差分放大器电路（AMP1）做放大差分输入信号V SP（t）和VSM（t）和到加法器电路（1B）那样生成加法信号Vfil（吨 ）通过加入斩波输出信号V子（t）的所做的斩波放大器（1）基因率。 输入到差分放大器电路（AMP 1）的差分信号被互换对于每一个第一相位周期和第二相位期间，和所述加法器电路（1B）基因速率通过加入在第一阶段期间的斩波器的输出信号的和在所述第二相加信号 相期。