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1.发明公开Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC 失效生产含有非易失性存储器单元和至少两种不同类型的外围晶体管电路的方法，和相应的集成电路
公开(公告)号：EP0751560A1
公开(公告)日：1997-01-02
申请号：EP95830282.0
申请日：1995-06-30
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) including an intermediate dielectric multilayer comprising a lower silicon oxide layer (7), an intermediate silicon nitride layer (8) and an upper silicon oxide layer (10) and the simultaneous provision in zones peripheral to the memory cells of at least one first (2) and one second (3) transistor type having gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer (5) and a polycrystalline silicon layer (6) and the formation of the lower silicon oxide layer (7) and of the intermediate silicon nitride layer (8), the process in accordance with the present invention includes:
removal of said layers from the zones peripheral (R2,R3) to the matrix;
formation of a first silicon oxide layer (9) over the substrate in the areas (R2,R3) of both types of transistor (2,3);
removal of the preceding layer (9) from areas (R3) assigned only to the transistors (3) of the second type;
deposition of said upper silicon oxide layer (10) over the memory cells (1), over the first silicon oxide layer (9) in the areas (R2) of the transistors (2) of the first type and over the substrate (4) in the areas (R3) of the transistors of the second type; and
formation of a second silicon oxide layer (11) in the areas (R2,R3) of both types of peripheral transistors (2,3).摘要翻译： 一种用于形成对集成电路工艺要求提供非易失性存储器单元（1）在中间电介质多层包括下氧化硅层（7）到中间氮化硅层（8）和在包括至少一个矩阵的 上部氧化硅层（10）和在区域中同时提供外围设备的至少一个第一（2）和第一和分别具有第二厚度的二分之一（3）晶体管类型的具有栅极电介质的存储器单元。 形成与栅极氧化物层（5）和多晶硅层（6）和所述下硅氧化层的形成单元的浮置栅极的后（7）和氮化物中间硅层（8），该方法的 在与本发明雅舞蹈包括：从所述外围区域（R2，R3）到基体中除去所述层的; 形成在这两种类型的晶体管的区域（R2，R3）的衬底（2,3）上的第一氧化硅层（9）的; 从仅分配给第二类型的晶体管（3）区域（R3）除去preceding-层（9）的; 在存储器单元所述氧化物上硅层（10）的沉积（1），在所述第一类型的晶体管（2）的在所述区域中的第一氧化硅层（9）（R2），并通过底物（4） 在第二类型的晶体管的区域（R3）; 和形成在这两种类型的外围晶体管（2,3）的所述区域（R2，R3）的第二硅氧化物层（11）的。
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2.发明公开Method of fabricating non-volatile memories, and non-volatile memory produced thereby 失效由此制备一种用于非易失性存储器的准备和存储的过程。
公开(公告)号：EP0591598A1
公开(公告)日：1994-04-13
申请号：EP92830541.6
申请日：1992-09-30
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546 , H01L29/42324 , H01L29/66825
摘要： A method comprising the steps of depositing a first (12) and second (17) polysilicon layer, separated by an oxide layer (13); selectively etching the second polysilicon layer (17) to form first gate regions (18); forming first substrate regions (26, 29) in the substrate (2) and laterally in relation to the first gate regions; selectively etching the first polysilicon layer (12) to form second gate regions of a length greater than the first gate regions (18); and forming in the substrate, laterally in relation to the second gate regions (12) and partially overlapping the first substrate regions (26, 29), second substrate regions (37, 38) of a higher doping level than the first substrate regions (26, 29).
摘要翻译： 一种方法，包括：沉积第一（12）和第二（17）的多晶硅层，通过在氧化物层（13）分离的步骤; 选择性地蚀刻所述第二多晶硅层（17），以形成第一栅极区域（18）; 在形成在基板（2）和相对于所述第一栅极区尾盘反弹第一区域的衬底（26，29）; 选择性地蚀刻所述第一多晶硅层（12），以形成（18）的长度比所述第一栅极区的更大的第二栅极区; 和相对于所述第二栅极区域（12），形成在所述基底，尾盘反弹和部分重叠的更高掺杂水平比所述第一基片区域的第一衬底的区域（26，29），第二基片的区域（37,38）（26 ，29）。
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3.发明授权EPROM cell with a readily scalable down interpoly dielectric 失效多晶硅层之间的EPROM单元Dielektricum，这是容易制造在小尺寸的
公开(公告)号：EP0571692B1
公开(公告)日：1998-07-22
申请号：EP92830266.0
申请日：1992-05-27
CPC分类号： H01L29/511 , Y10S148/114
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4.发明公开Process of fabricating non-volatile floating-gate memory devices, and memory device fabricated thereby 失效一种制备非易失性存储器设备，浮动栅极存储器装置并检测由此制备过程
公开(公告)号：EP0788168A1
公开(公告)日：1997-08-06
申请号：EP96830040.0
申请日：1996-01-31
IPC分类号： H01L29/423 , H01L21/336 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/42328 , H01L29/66825
摘要： A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region (20), a dielectric region (21), and a control gate region (22); and forming an insulating layer (35) of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer (35) is formed during reoxidation of the sides of the floating gate region (20), after self-align etching the stack of layers (20-22) and implanting the source/drain of the cell.
摘要翻译： 制造浮动栅极存储器装置的方法，该方法包括以下步骤：形成叠置的层包含一浮动栅极区（20），介电区域（21），和控制栅极区域（22）的堆叠; 以及形成绝缘氧氮化物的层（35）到浮栅区域的一侧完全呼叫向外密封浮栅区，提高了存储装置的保持特性的。 在绝缘层（35）的浮置栅极区域（20）的侧面的再氧化过程中形成，之后自对准蚀刻层的堆叠（20-22）和注入单元的源极/漏极。
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5.发明公开Method of fabricating integrated devices, and integrated device produced thereby 失效集成器件的制备方法，以及由此制备的集成器件。
公开(公告)号：EP0591599A1
公开(公告)日：1994-04-13
申请号：EP92830542.4
申请日：1992-09-30
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L27/11526 , H01L21/823842 , H01L27/0922 , H01L27/105 , H01L27/11546
摘要： A method comprising the steps of depositing a first (12) and second (17) polysilicon layer, separated by an oxide layer (13); selectively etching the second polysilicon layer (17) to form first gate regions (18); forming first substrate regions (26, 29) in the substrate (2) and laterally in relation to the first gate regions; selectively etching the first polysilicon layer (12) to form second gate regions of a length greater than the first gate regions (18); and forming, in the substrate, laterally in relation to the second gate regions (12) and partially overlapping the first substrate regions (26, 29), second substrate regions (37, 38) of a higher doping level than the first substrate regions (26, 29).
摘要翻译： 一种方法，包括：沉积第一（12）和第二（17）的多晶硅层，通过在氧化物层（13）分离的步骤; 选择性地蚀刻所述第二多晶硅层（17），以形成第一栅极区域（18）; 在形成在基板（2）和相对于所述第一栅极区尾盘反弹第一区域的衬底（26，29）; 选择性地蚀刻所述第一多晶硅层（12），以形成（18）的长度比所述第一栅极区的更大的第二栅极区; 和形成，在底物，尾盘反弹相对于所述第二栅极区域（12）和部分重叠的更高掺杂水平比所述第一基片区域的第一衬底的区域（26，29），第二基板区域（37，38）（ 26，29）。
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6.发明公开A method of manufacturing a MOS integrated circuit having components with different dielectrics 失效对于具有不同Dielektrum部件的集成电路制造工艺
公开(公告)号：EP0752717A1
公开(公告)日：1997-01-08
申请号：EP95830189.7
申请日：1995-05-10
IPC分类号： H01L21/00 , H01L21/8247 , H01L21/8242 , H01L27/105
CPC分类号： H01L27/11526 , H01L21/3145 , H01L27/105 , H01L27/1052 , H01L27/10844 , H01L27/11539
摘要： The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To improve the quality of the oxide of the cells essentially in terms of resistance to degradation due to the passage of charges through it during the operation of the memory, the method provides for a step for the high-temperature nitriding of the oxide. According to a variant, the nitrided oxide formed on the areas intended for the components of the peripheral circuits is removed and then formed again by a similar thermal oxidation treatment followed by high-temperature nitriding.
摘要翻译： 描述的方法提供用于薄的热氧化物上拟用于存储器单元和存储器的外围电路的其它部件的硅的区域的形成。 为了提高细胞的氧化物的基本上对降解的抗性的方面的质量由于通过它的电荷存储器的外科手术过程中的通道中，该方法提供了用于在氧化物的高温氮化的工序。 。根据一个变型中，形成在旨在用于外围电路的部件的区域中的氮化的氧化被除去，然后通过随后的高温氮化相似的热氧化处理再次形成。
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7.发明公开Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC 失效包含非易失性存储器单元和外围晶体管，和相应的类型的集成电路的电路的制造方法
公开(公告)号：EP0751559A1
公开(公告)日：1997-01-02
申请号：EP95830281.2
申请日：1995-06-30
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) having an intermediate dielectric multilayer including at least a lower dielectric material layer (8) and an upper silicon oxide layer (9) and the simultaneous provision in zones peripheral to the matrix of at least one first transistor type (2) having gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer (4) and a polycrystalline silicon layer (5) and the formation of the lower dielectric material layer (8), the process in accordance with the present invention calls for:
removal of said layers from the peripheral zones (R2) of the matrix;
deposition of said upper silicon oxide layer (9) over the memory cells (1),and over the substrate (3) in the areas (R2) of the peripheral transistors (2); and
formation of a first silicon oxide layer (10) at least in the areas (R2) of the peripheral transistors (2).
To provide additionally a second transistor type having gate dielectric of a second thickness, indicatively thinner than said first thickness, successive steps are added in accordance with the present invention.摘要翻译： 一种用于形成对集成电路工艺要求提供（1）在中间电介质多层具有包含非易失性存储器单元中的至少一个矩阵的至少一个下电介质材料层（8），并在上部氧化硅层（9） 和在区域周向具有第一厚度的栅极介电的至少一个第一晶体管类型（2）的基体中的同时提供。 与栅极氧化物层（4）和多晶硅层（5）和下电介质材料层的形成在形成浮置栅极之后（8），在雅舞蹈过程与本发明要求：去除所述层的 从基体的外周区域（R2）; 说，在存储单元（1）上的氧化硅层（9）的沉积，并用在外围晶体管（2）的区域（R2）的基板（3）; 和形成在外围晶体管（2）的区域（R2）的至少一个第一氧化硅层（10）的。 以提供另外具有第二厚度的栅极介电的第二晶体管的类型，指示性比所述第一厚度薄，在雅舞蹈添加与本发明的连续步骤。
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8.发明公开EPROM cell with a readily scalable down interpoly dielectric 失效EPROM-Zelle mit Dielektricum zwischen Polysiliziumschichten，das leicht in kleinen Dimensionen herstellbar ist。
公开(公告)号：EP0571692A1
公开(公告)日：1993-12-01
申请号：EP92830266.0
申请日：1992-05-27
CPC分类号： H01L29/511 , Y10S148/114
摘要： The use of an O-N-RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O-N-O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling down.
摘要翻译： 在可程序的只读存储器单元的浮动栅结构中使用ON-RTN（氧化氮 - 氮化物 - 快速热氮化多晶硅）多层电介质多层代替常规的ONO（氧化物 - 氮化物 - 氧化物）多层，具有有益的效果 关于电池的性能，并有助于其缩小。
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