公开(公告)号：EP3033767A4

公开(公告)日：2017-03-22

申请号：EP14835785

申请日：2014-07-24

申请人： MICRON TECHNOLOGY INC

发明人： JAYANTI SRIKANT ,  SIMSEK-EGE FATMA ARZUM ,  AELLA PAVAN KUMAR REDDY

IPC分类号： H01L27/11556 ,  H01L21/28 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/8239 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/16 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

摘要： Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

摘要翻译： 半导体结构可以包括交替介电材料和控制栅极的堆叠，横向邻近控制栅极的电荷存储结构，电荷存储结构和横向相邻控制栅极之间的电荷块材料，以及延伸穿过堆叠 交替氧化物材料和控制门。 堆叠中的每个介电材料具有不同密度和/或不同的去除速率的至少两个部分。 还公开了制造这种半导体结构的方法。

公开(公告)号：EP2639818A3

公开(公告)日：2017-01-18

申请号：EP13157686.0

申请日：2013-03-04

申请人： Renesas Electronics Corporation

发明人： Kaneoka, Tatsunori ,  Kawahara, Takaaki

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L27/1157 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode (MG) is formed over a semiconductor substrate (1) via an insulating film (5). The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film (5a), a silicon nitride film (5b) over the first silicon oxide film, and a second silicon oxide film (5c) over the silicon nitride film. Metal elements (6) exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1 × 10 13 to 2 × 10 14 atoms/cm 2 .

摘要翻译： 提供具有非易失性存储器的半导体器件，其具有改善的电性能。 存储栅电极（MG）经由绝缘膜（5）形成在半导体衬底（1）上。 绝缘膜是其中具有电荷存储部分的绝缘膜，并且在第一氧化硅膜上方包括第一氧化硅膜（5a），氮化硅膜（5b）和第二氧化硅膜（5c） 氮化硅膜。 在氮化硅膜和第二氧化硅膜之间存在金属元素（6），或者在氮化硅膜中以1×10 13至2×10 14原子/ cm 2的表面密度存在金属元素（6）。

公开(公告)号：EP3033767A1

公开(公告)日：2016-06-22

申请号：EP14835785.8

申请日：2014-07-24

申请人： Micron Technology, Inc.

发明人： JAYANTI, Srikant ,  SIMSEK-EGE, Fatma Arzum ,  AELLA, Pavan Kumar Reddy

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/8239 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/16 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

摘要： Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

公开(公告)号：EP2988331A1

公开(公告)日：2016-02-24

申请号：EP15188426.9

申请日：2001-08-13

申请人： SanDisk 3D LLC

发明人： LEE, Thomas H. ,  SUBRAMANIAN, Vivek ,  CLEEVES, James M. ,  WALKER, Andrew J. ,  PETTI, Christopher ,  KOUZNETZOV, Igor G. ,  JOHNSON, Mark G. ,  FARMWALD, Paul M. ,  HERNER, Brad

IPC分类号： H01L27/115 ,  G11C16/34 ,  H01L21/822 ,  H01L29/423 ,  H01L29/66 ,  H01L27/06 ,  H01L29/788 ,  H01L29/792 ,  H01L27/12 ,  H01L29/861 ,  H01L27/112 ,  H01L29/16

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续器件级之间的至少一个表面平坦化。

公开(公告)号：EP1107304B1

公开(公告)日：2008-06-18

申请号：EP00310522.8

申请日：2000-11-27

申请人： Agere Systems Optoelectronics Guardian Corporation

发明人： Schneemeyer, Lynn Frances ,  Van Dover, Robert Bruce

IPC分类号： H01L21/316 ,  H01L21/02 ,  H01L29/92 ,  H01L27/108

CPC分类号： H01L21/28194 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L27/1085 ,  H01L29/511 ,  H01L29/517

公开(公告)号：EP1856724A2

公开(公告)日：2007-11-21

申请号：EP06720394.3

申请日：2006-02-08

申请人： Freescale Semiconductor, Inc.

发明人： LIM, Sangwoo ,  GRUDOWSKI, Paul, A. ,  LUO, Tien, Ying ,  ADETUTU, Olubunmi, O. ,  TSENG, Hsing, H.

IPC分类号： H01L21/3205 ,  H01L21/31 ,  H01L21/336

CPC分类号： H01L21/02329 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/6659 ,  H01L29/7833

摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.

公开(公告)号：EP1226606B1

公开(公告)日：2007-02-21

申请号：EP00980252.1

申请日：2000-11-01

申请人： Infineon Technologies North America Corp.

发明人： VOLLRATH, Joerg

IPC分类号： H01L21/762

CPC分类号： H01L21/28158 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/66568

摘要： A method for forming spacers for preventing formation of parasitic corner devices in transistors includes etching trenches into a semiconductor substrate to form an active area region, lining the trenches and the active area region with a first dielectric material and forming shallow trench isolation regions adjacent to the active area region by filling the trenches with a second dielectric material. The first dielectric material is removed from the active area region, and a gate oxide is formed over the active area region wherein divots form between the active area region and the shallow trench isolation regions. Dopants are implanted into the active area region to form a source and drain of the transistor. After the step of implanting, a spacer layer formed from a third dielectric material is deposited over the gate oxide layer to fill the divots. Anisotropically etching of the spacer layer forms spacers in the divots such that gate conductor material is prevented from entering the divots and the gate conductor material is spaced apart from corners of the active area region by the spacers to prevent the formation of the parasitic corner devices.

公开(公告)号：EP1204992B1

公开(公告)日：2006-09-13

申请号：EP00945560.1

申请日：2000-05-23

申请人： Infineon Technologies AG

发明人： LARIK, Joost ,  HIRLER, Franz ,  KOTEK, Manfred

IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7811

摘要： The invention relates to a method for producing a trench MOS power transistor in which an oxide step (20) is produced between a thicker oxide layer (5) and a thinner oxide layer (5') by means of an auxiliary layer (6) placed in a trench (2) of an epitactical layer (3).

公开(公告)号：EP1362332B1

公开(公告)日：2005-03-02

申请号：EP02700209.6

申请日：2002-01-31

申请人： Infineon Technologies AG

发明人： PALM, Herbert ,  WOHLRAB, Erdmute ,  TADDIKEN, Hans

IPC分类号： G07F1/00 ,  H01L29/423

CPC分类号： H01L29/511 ,  G04F1/005 ,  G04F10/10 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/792

摘要： The invention relates to a time-detection device using a floating-gate-cell, wherein an ON-layer structure or a ONO-layer structure is provided between the floating-gate and the control-gate. A charge injection device is supplied in order to insert the floating-gate-electrode into the nitride layer of the ON-structure or the ONO-layer structure, wherein a voltage or a voltage pulse is applied to the control-gate-electrode, the centre of gravity of the charges injected into the nitride layer being located on the defining surface. Said time-detection device also comprises a device for detecting time elapsed since injection of the charges, based on changes in the transmission behaviour of the channel area, which are effected by displacement of the centre of gravity of the charges in the nitride layer away from the defining surface.

公开(公告)号：EP1226606A1

公开(公告)日：2002-07-31

申请号：EP00980252.1

申请日：2000-11-01

申请人： Infineon Technologies North America Corp.

发明人： VOLLRATH, Joerg

IPC分类号： H01L21/762

CPC分类号： H01L21/28158 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/66568

摘要： A method for forming spacers for preventing formation of parasitic corner devices in transistors includes etching trenches into a semiconductor substrate to form an active area region, lining the trenches and the active area region with a first dielectric material and forming shallow trench isolation regions adjacent to the active area region by filling the trenches with a second dielectric material. The first dielectric material is removed from the active area region, and a gate oxide is formed over the active area region wherein divots form between the active area region and the shallow trench isolation regions. Dopants are implanted into the active area region to form a source and drain of the transistor. After the step of implanting, a spacer layer formed from a third dielectric material is deposited over the gate oxide layer to fill the divots. Anisotropically etching of the spacer layer forms spacers in the divots such that gate conductor material is prevented from entering the divots and the gate conductor material is spaced apart from corners of the active area region by the spacers to prevent the formation of the parasitic corner devices.