公开(公告)号：EP0846996A1

公开(公告)日：1998-06-10

申请号：EP96830610.0

申请日：1996-12-05

申请人： SGS-THOMSON MICROELECTRONICS s.r.l. ,  MAGNETI MARELLI S.p.A.

发明人： Milanesi, Andrea ,  Poletto, Vanni ,  Poma, Alberto ,  Morelli, Marco

IPC分类号： G05F1/575

CPC分类号： G05F1/575

摘要： A voltage-regulator circuit with a low voltage drop using a DMOS power transistor (PT) driven by a charge pump (CP) comprises two feedback loops: a first feedback loop having high gain and accuracy but low response speed, and a second feedback loop having a wide passband and fast response speed but low gain.

摘要翻译： 使用由电荷泵（CP）驱动的DMOS功率晶体管（PT）具有低压降的电压调节器电路包括两个反馈回路：具有高增益和精度但响应速度低的第一反馈环路和第二反馈回路 具有宽通带和快速响应速度但低增益。

公开(公告)号：EP0851585A1

公开(公告)日：1998-07-01

申请号：EP96830650.6

申请日：1996-12-24

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Milanesi, Andrea

IPC分类号： H03K17/284 ,  H03K17/14 ,  G05F3/24

CPC分类号： H03K17/284 ,  G05F3/242

摘要： A circuit for the generation of an electrical signal of constant duration comprises a capacitor (C), a constant current generator for charging said capacitor and a voltage comparator (COMP) to compare the voltage present at the terminals of the capacitor with a reference voltage (V ref ) and supply at output a digital signal (OUT) dependent upon the voltage across the capacitor; the constant current generator comprises a transistor (M1) biased with a voltage (V gsx) between gate and source obtained as the difference between the sum of two gate-source voltages of two transistors (M2,M3) and a gate-source voltage of another transistor (M4).

摘要翻译： 一种用于恒定的持续时间的电气信号的发生电路包括一个电容器（C），恒流发生器，用于充电所述电容器和一个电压比较器（COMP）比较存在于电容器的与基准电压端子处的电压（ V REF）和电源在输出的数字信号（OUT）取决于电容器两端的电压; 恒定电流发生器包括晶体管（M1）被偏置以获得作为两个晶体管（M2，M3）和另一个的栅 - 源电压的两个栅极 - 源极电压的总和之间的差的栅极和源极之间的电压（Vgsx） 晶体管（M4）。

公开(公告)号：EP1052518A1

公开(公告)日：2000-11-15

申请号：EP99830294.7

申请日：1999-05-13

申请人： STMicroelectronics S.r.l. ,  MAGNETI MARELLI S.p.A.

发明人： Milanesi, Andrea ,  Chicca, Stefania ,  Poletto, Vanni ,  Giorgetta, Valerio ,  Sgatti, Stefano ,  Vigna, Sergio

IPC分类号： G01R31/02

CPC分类号： G01R31/024

摘要： A system is described for the diagnosis of a driver (D) of the type adapted to detect one or more circuit anomalies which can occur in the said driver, including:

voltage comparator circuits (10, 20) adapted to generate diagnostic logic signals (F 1 , F 2 , F 3 ) each indicative of the existence of a corresponding type of anomaly; and
a coding circuit (M, SM) adapted to receive these diagnostic signals (F 1 , F 2 , F 3 ) and to output information relating to an overall operating state of the circuit. The coding circuit (M, SM) includes a first portion adapted to provide at its output first logic signals (SHB, SHG, OL) indicative of the last anomaly occurred since a system reset operation, and a second portion for coding such first logic signals (SHB, SHG, OL). The second portion includes a sequential logic network (SM) adapted to:


receive the first logic input signals (SHB, SHG, OL) and at least one second logic signal (IN) indicative of the current operating phase of the driver (D); and
achieve, as a function of the said first and second logic signals (SHB, SHG, OL; IN) a stable internal state such as to determine at the output information in the form of an N bit coded word representative of an occurred anomaly, of a condition of absence of anomaly in the current operating phase, or of a condition of absence of anomaly in any operating phase.

摘要翻译： 描述了用于诊断适于检测可能发生在所述驱动器中的一个或多个电路异常的类型的驱动器（D）的系统，包括：适于产生诊断逻辑信号的电压比较器电路（10,20）（F1 ，F2，F3），每个指示存在相应类型的异常; 以及适于接收这些诊断信号（F1，F2，F3）的编码电路（M，SM），并且输出与电路的总体工作状态有关的信息。 编码电路（M，SM）包括适于在其输出端提供指示自系统复位操作以来发生的最后异常的第一逻辑信号（SHB，SHG，OL）的第一部分和用于对这些第一逻辑信号进行编码的第二部分 （SHB，SHG，OL）。 第二部分包括适于：接收第一逻辑输入信号（SHB，SHG，OL）的顺序逻辑网络（SM）和指示驾驶员（D）的当前操作阶段的至少一个第二逻辑信号（IN）; 并且作为所述第一和第二逻辑信号（SHB，SHG，OL; IN）的函数实现稳定的内部状态，例如以表示发生的异常的N位编码字的形式在输出信息处确定， 在当前运行阶段没有异常的情况，或任何运行阶段没有异常的情况。