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公开(公告)号：EP0674785B1
公开(公告)日：1997-11-12
申请号：EP94901770.1
申请日：1993-12-17
发明人： ABERT, Michael , BLOCK, Siegfried , BOZENHARDT, Johannes , LEIGSNERING, Franz , PFATTEICHER, Werner , SCHEWE, Franz-Clemens
IPC分类号： G06F13/24
CPC分类号： G06F13/4072 , G05B19/0423 , G06F13/24
摘要： The invention relates to an arrangement with a plurality of plug points (SP1, ..., SP4) which are interconnected via a system bus (SYB) with data and control lines and into which at least one CPU (CP) is plugged and a plurality of functional peripheral devices (PE1, PE2, PE4) can be plugged. The arrangement is constructed in such a way that the CPU (CP) rapidly recognises a plugged-in in unit triggering an alarm. The invention is applicable to store programmable controls.
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公开(公告)号：EP0667014B1
公开(公告)日：1998-01-07
申请号：EP93923453.0
申请日：1993-10-29
发明人： ABERT, Michael , BLOCK, Siegfried , BOZENHARDT, Johannes , LEIGSNERING, Franz , PFATTEICHER, Werner , SCHEWE, Franz-Clemens
IPC分类号： G06F13/378
CPC分类号： G06F13/368 , G06F13/378
摘要： The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.
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公开(公告)号：EP0739509B1
公开(公告)日：1997-02-26
申请号：EP95920763.0
申请日：1995-06-06
CPC分类号： G06F13/1605 , G05B19/0421 , G05B2219/2231 , G05B2219/25217
摘要： The invention relates to an arrangement with at least one master unit connected via a bus to slave units, each having a store in which the master unit performs read and/or write operations. Suitable means make it possible for the master unit to initialise data access uniformly on each of the slave units according to a predetermined communication protocol. The proposal is also for a slave unit which is suitable for communication with a master unit according to said protocol. The invention is used in automation devices.
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公开(公告)号：EP0671033A1
公开(公告)日：1995-09-13
申请号：EP94900046.0
申请日：1993-11-18
发明人： ABERT, Michael , BLOCK, Siegfried , BOZENHARDT, Johannes , LEIGSNERING, Franz , PFATTEICHER, Werner , SCHEWE, Franz-Clemens
CPC分类号： G06F13/4018
摘要： An arrangement for transmitting data over a bus (2, 6, 7) has a central unit (1, 4, 5) which initiates data transmission and one or several peripheral units (3, 8, 9) linked to each other by the bus. In at least one of the components, besides first control lines and data lines for transmitting a data word having a first data width, further control lines and further data lines for transmitting a data word having a second data width are also provided. These are designed in such a way that components with different data bus widths can communicate with each other by transmission of data words having the smallest existent data width. In automation equipment, the invention allows any combination of components of different classes of capacity. The invention is used in bus systems.
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公开(公告)号：EP0667014A1
公开(公告)日：1995-08-16
申请号：EP93923453.0
申请日：1993-10-29
发明人： ABERT, Michael , BLOCK, Siegfried , BOZENHARDT, Johannes , LEIGSNERING, Franz , PFATTEICHER, Werner , SCHEWE, Franz-Clemens
IPC分类号： G06F13
CPC分类号： G06F13/368 , G06F13/378
摘要： The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.
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公开(公告)号：EP0670062B1
公开(公告)日：1997-09-17
申请号：EP93924525.4
申请日：1993-11-18
发明人： ABERT, Michael , BLOCK, Siegfried , BOZENHARDT, Johannes , LEIGSNERING, Franz , PFATTEICHER, Werner , SCHEWE, Franz-Clemens
IPC分类号： G06F12/06
CPC分类号： G06F12/0661
摘要： The proposal is for an arrangement with a plurality of plug points (SP1, ...) which are interconnected via a system bus (SYB) having data and control lines, address lines (AL1, ...) taken to connections of the plug points (SP1, ...), one of which is connected to a selector terminal (AN1, ...), and plug-in functional units (FE1, ...), at least one (FE1; FE3) of which has means for connecting the address lines (AL1, ...) to this unit and each of the remaining functional units (FE2; FE4) has means for connecting the unit to the selector terminal (AN1, ...) of the plug point. Units performing read and write functions can be fitted at any plug point in such an arrangement. The invention is applicable in store-programmable controls.
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公开(公告)号：EP0670062A1
公开(公告)日：1995-09-06
申请号：EP93924525.0
申请日：1993-11-18
发明人： ABERT, Michael , BLOCK, Siegfried , BOZENHARDT, Johannes , LEIGSNERING, Franz , PFATTEICHER, Werner , SCHEWE, Franz-Clemens
IPC分类号： G06F12
CPC分类号： G06F12/0661
摘要： The proposal is for an arrangement with a plurality of plug points (SP1, ...) which are interconnected via a system bus (SYB) having data and control lines, address lines (AL1, ...) taken to connections of the plug points (SP1, ...), one of which is connected to a selector terminal (AN1, ...), and plug-in functional units (FE1, ...), at least one (FE1; FE3) of which has means for connecting the address lines (AL1, ...) to this unit and each of the remaining functional units (FE2; FE4) has means for connecting the unit to the selector terminal (AN1, ...) of the plug point. Units performing read and write functions can be fitted at any plug point in such an arrangement. The invention is applicable in store-programmable controls.
摘要翻译： 该建议是针对具有多个插入点（SP1，...）的布置，所述插入点经由系统总线（SYB）互连，所述系统总线具有数据线和控制线，地址线（AL1，...） 其中一个连接到选择器端子（AN1，...）的点（SP1，...）和插入功能单元（FE1，...），其中至少一个（FE1; FE3） 具有用于将地址线（AL1，...）连接到该单元并且每个其余功能单元（FE2; FE4）具有用于将该单元连接到插头点的选择器端子（AN1，...） 。 执行读写功能的单元可以安装在任何插入点。 本发明适用于商店可编程控制。
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公开(公告)号：EP0669027A1
公开(公告)日：1995-08-30
申请号：EP93924020.0
申请日：1993-11-04
发明人： ABERT, Michael , BLOCK, Siegfried , BOZENHARDT, Johannes , LEIGSNERING, Franz , PFATTEICHER, Werner , SCHEWE, Franz-Clemens
CPC分类号： G06F12/0653 , G06F13/4208
摘要： The invention relates to an arrangement for transmitting data via a bus with a central unit and a plurality of peripheral units connected to the bus, to each of which a physical address field of predetermined size is allocated via plug point addressing. A programmable conversion unit (1) allocates to logic addresses used in the central unit the corresponding physical addresses. Thus gaps in the physical address field caused by the geographical addressing process has no effect on the addresses of the user program and the process data can be given sequential logic addresses. The invention is applicable in bus systems.
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公开(公告)号：EP0667015A1
公开(公告)日：1995-08-16
申请号：EP93924011.0
申请日：1993-10-29
发明人： ABERT, Michael , BLOCK, Siegfried , BOZENHARDT, Johannes , LEIGSNERING, Franz , PFATTEICHER, Werner , SCHEWE, Franz-Clemens
IPC分类号： G06F13
CPC分类号： G06F13/378 , G06F13/1652 , G06F13/368
摘要： The invention pertains to a configuration with several active and passive bus users (MP1, MP2, SP1, SP2), each of which is allocated a memory (S1, S2, SS1, SS2), with its own memory area (SB1, SB2, SB3, SB4), where each bus user (MP1, MP2, SP1, SP2) has read access to its own memory area (SB1, SB2, SB3, SB4) and each active bus user (MP1, MP2) has write access to every memory area (SB1, SB2, SB3, SB4). A control line (ML) is provided for sending an indicative signal (SR) which indicates to the active bus users (MP1, MP2) accessing the memory areas (SB1, SB2, SB3, SB4) whether data in the memory areas (SB1, SB2, SB3, SB4) have already been written in, as the answering signal (SR) has dominant and recessive statuses and outside of access cycles all bus users produce a dominant status, during a cycle of access to the memory areas (SB1, SB2, SB3, SB4) only the bus users (MP1, MP2, SP1, SP2) in whose memory areas (SB1, SB2, SB3, SB4) the data have not yet been written in produce such a signal. The invention is used in automation systems.
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10.发明授权VERFAHREN ZUR ÜBERTRAGUNG VON DATEN ÜBER EINE DATENÜBERTRAGUNGSEINHEIT UND DATENVERARBEITUNGSANLAGE 有权方法用于将数据通过数据传输单元和数据处理系统传输
公开(公告)号：EP1405194B1
公开(公告)日：2004-11-03
申请号：EP02753004.7
申请日：2002-07-09
发明人： ABERT, Michael
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06Q20/382
摘要： The invention relates to a method for transmitting data (D) in a particularly simple, secure and rapid manner, in accordance with various requirements, on a single data transmission unit. According to the inventive method for transmitting data (D) between data processing units (2,4) of a data processing system (1) via a data transmission unit, data (D) is transmitted in a parallel manner in at least two protocols. The first protocol enables data (D) to be transmitted within a first frequency range with a first signal sequence and a first signal level. The second protocol enables other data (D) to be transmitted within a second frequency range with a second signal sequence and a second signal level.
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