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    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN
    2.
    发明公开
    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN 失效
    ANORDNUNG MIT STECKBAREN FUNKTION SEINHEITEN

    公开(公告)号：EP0674785A1

    公开(公告)日：1995-10-04

    申请号：EP94901770.0

    申请日：1993-12-17

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G05B19 ,  G06F13

    CPC分类号： G06F13/4072 ,  G05B19/0423 ,  G06F13/24

    摘要： The invention relates to an arrangement with a plurality of plug points (SP1, ..., SP4) which are interconnected via a system bus (SYB) with data and control lines and into which at least one CPU (CP) is plugged and a plurality of functional peripheral devices (PE1, PE2, PE4) can be plugged. The arrangement is constructed in such a way that the CPU (CP) rapidly recognises a plugged-in in unit triggering an alarm. The invention is applicable to store programmable controls.

    摘要翻译： 本发明涉及一种具有多个插接点（SP1，...，SP4）的装置，所述插接点通过系统总线（SYB）与数据线和控制线互连并且至少一个CPU（CP）被插入其中并且a 可以插入多个功能外围设备（PE1，PE2，PE4）。 这种安排的构造方式使得CPU（CP）能够快速识别出触发警报的插入单元。 本发明适用于存储可编程控制。

    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM
    4.
    发明授权
    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM 失效
    安排了并行总线系统中数据传输

    公开(公告)号：EP0667014B1

    公开(公告)日：1998-01-07

    申请号：EP93923453.0

    申请日：1993-10-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13/378

    CPC分类号： G06F13/368 ,  G06F13/378

    摘要： The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.

    ANORDNUNG ZUR ÜBERTRAGUNG VON DATEN ÜBER EINEN BUS
    5.
    发明公开
    ANORDNUNG ZUR ÜBERTRAGUNG VON DATEN ÜBER EINEN BUS 失效
    安排用于数据上的总线传输。

    公开(公告)号：EP0671033A1

    公开(公告)日：1995-09-13

    申请号：EP94900046.0

    申请日：1993-11-18

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F3 ,  G06F13

    CPC分类号： G06F13/4018

    摘要： An arrangement for transmitting data over a bus (2, 6, 7) has a central unit (1, 4, 5) which initiates data transmission and one or several peripheral units (3, 8, 9) linked to each other by the bus. In at least one of the components, besides first control lines and data lines for transmitting a data word having a first data width, further control lines and further data lines for transmitting a data word having a second data width are also provided. These are designed in such a way that components with different data bus widths can communicate with each other by transmission of data words having the smallest existent data width. In automation equipment, the invention allows any combination of components of different classes of capacity. The invention is used in bus systems.

    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM
    6.
    发明公开
    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM 失效
    安排了并行总线系统中数据传输。

    公开(公告)号：EP0667014A1

    公开(公告)日：1995-08-16

    申请号：EP93923453.0

    申请日：1993-10-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13

    CPC分类号： G06F13/368 ,  G06F13/378

    摘要： The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.

    ANORDNUNG ZUR ÜBERTRAGUNG VON DATEN ÜBER EINEN BUS
    7.
    发明授权
    ANORDNUNG ZUR ÜBERTRAGUNG VON DATEN ÜBER EINEN BUS 失效
    安排用于数据上的总线传输

    公开(公告)号：EP0671033B1

    公开(公告)日：1998-07-22

    申请号：EP94900046.7

    申请日：1993-11-18

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4018

    摘要： An arrangement for transmitting data over a bus (2, 6, 7) has a central unit (1, 4, 5) which initiates data transmission and one or several peripheral units (3, 8, 9) linked to each other by the bus. In at least one of the components, besides first control lines and data lines for transmitting a data word having a first data width, further control lines and further data lines for transmitting a data word having a second data width are also provided. These are designed in such a way that components with different data bus widths can communicate with each other by transmission of data words having the smallest existent data width. In automation equipment, the invention allows any combination of components of different classes of capacity. The invention is used in bus systems.

    ANORDNUNG MIT MEHREREN AKTIVEN UND PASSIVEN BUSTEILNEHMERN
    10.
    发明授权
    ANORDNUNG MIT MEHREREN AKTIVEN UND PASSIVEN BUSTEILNEHMERN 失效
    具有多个活动和被动站安排

    公开(公告)号：EP0667015B1

    公开(公告)日：1997-03-05

    申请号：EP93924011.5

    申请日：1993-10-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13/378 ,  G06F13/368

    CPC分类号： G06F13/378 ,  G06F13/1652 ,  G06F13/368

    摘要： The invention pertains to a configuration with several active and passive bus users (MP1, MP2, SP1, SP2), each of which is allocated a memory (S1, S2, SS1, SS2), with its own memory area (SB1, SB2, SB3, SB4), where each bus user (MP1, MP2, SP1, SP2) has read access to its own memory area (SB1, SB2, SB3, SB4) and each active bus user (MP1, MP2) has write access to every memory area (SB1, SB2, SB3, SB4). A control line (ML) is provided for sending an indicative signal (SR) which indicates to the active bus users (MP1, MP2) accessing the memory areas (SB1, SB2, SB3, SB4) whether data in the memory areas (SB1, SB2, SB3, SB4) have already been written in, as the answering signal (SR) has dominant and recessive statuses and outside of access cycles all bus users produce a dominant status, during a cycle of access to the memory areas (SB1, SB2, SB3, SB4) only the bus users (MP1, MP2, SP1, SP2) in whose memory areas (SB1, SB2, SB3, SB4) the data have not yet been written in produce such a signal. The invention is used in automation systems.