公开(公告)号：EP0889517A1

公开(公告)日：1999-01-07

申请号：EP98109831.2

申请日：1998-05-29

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Alsmeier, Johann ,  Wangemann, Klaus

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/763

CPC分类号： H01L21/763 ,  H01L21/823878 ,  H01L27/0921

摘要： A complementary metal oxide (CMOS) integrated circuit configured for reducing the formation of silicon defects in its silicon substrate during manufacture. The silicon defects are formed from silicon interstitials present in the silicon substrate. The CMOS integrated circuit includes a deep implantation region formed within the silicon substrate. There is further included at least one vertical trench formed in the silicon substrate. The trench is formed such that at least a portion of the trench penetrates into the deep implantation region of the silicon substrate to present vertical surfaces within the deep implantation region, thereby allowing the silicon interstitials to recombine at the vertical surfaces.

摘要翻译： 互补金属氧化物（CMOS）集成电路，其被配置为在制造期间减少其硅衬底中的硅缺陷的形成。 硅缺陷由存在于硅衬底中的硅间隙形成。 CMOS集成电路包括形成在硅衬底内的深注入区域。 还包括在硅衬底中形成的至少一个垂直沟槽。 沟槽形成为使得沟槽的至少一部分穿透到硅衬底的深注入区域中以在深注入区域内呈现垂直表面，从而允许硅间隙在垂直表面处复合。