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24 条记录 (耗时 0.01 秒)

    Trench capacitor dram cell with vertical transistor
    1.
    发明公开
    Trench capacitor dram cell with vertical transistor 失效
    DRAM-Zelle mit Graben-Kondensator和Vertikalem晶体管

    公开(公告)号：EP0884785A3

    公开(公告)日：2001-10-10

    申请号：EP98109684.5

    申请日：1998-05-28

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A vertical transistor used in a memory cell, such as a DRAM cell, having a trench capacitor. The vertical transistor comprises a gate which includes a horizontal portion (253) and a vertical portion (245) located above the trench capacitor.

    摘要翻译： 在具有沟槽电容器的诸如DRAM单元的存储单元中使用的垂直晶体管。 垂直晶体管包括一个栅极，该栅极包括位于沟槽电容器上方的水平部分和垂直部分。

    Trench capacitor DRAM cell
    2.
    发明公开
    Trench capacitor DRAM cell 失效
    Grabenkondensator-DRAM-Zelle

    公开(公告)号：EP0822599A2

    公开(公告)日：1998-02-04

    申请号：EP97305280.6

    申请日：1997-07-15

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann ,  Mandelman, Jack Allan ,  O'Neill, James Anthony ,  Parks, Christopher ,  Parries, Paul Christian

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10829

    摘要： The preferred embodiment provides an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor. The inversion layer is created by forming a trench capacitor in a lightly doped substrate. With a sufficient workfunction difference between the storage node material and the isolation band the surface of the lightly doped substrate inverts, with the inversion charge being supplied by the isolation band. This inversion layer serves as the plate counter electrode for the capacitor.

    摘要翻译： 优选实施例提供一种集成电路电容器，其通过使用基板中的反转层作为用于电容器的板对电极来实现高电容。 通过在轻掺杂衬底中形成沟槽电容器来产生反型层。 在存储节点材料和隔离带之间具有足够的功函数差异时，轻掺杂衬底的表面反转，反转电荷由隔离带提供。 该反转层用作电容器的平板对置电极。

    Trench capacitor DRAM cell
    3.
    发明公开
    Trench capacitor DRAM cell 失效
    Herstellungsverfahrenfüreine Grabenkondensator-DRAM-Zelle

    公开(公告)号：EP0713253A1

    公开(公告)日：1996-05-22

    申请号：EP95116061.3

    申请日：1995-10-11

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann ,  Gall, Martin

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832

    摘要： A DRAM unit cell is disclosed which comprises a trench capacitor (23,25,24) having a signal electrode (24), a bit line (28), a planar active word line (36) overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the trench capacitor and the bit line and a gate electrode formed by the active word line.
    The unit cell takes up a smaller substrate area than prior art unit cells because of the overlap between the word line and the trench capacitor.

    摘要翻译： 公开了一种DRAM单元，其包括具有信号电极（24）的沟槽电容器（23,25,24），位线（28），与沟槽电容器重叠的平面有源字线（36）和具有 耦合在沟槽电容器的信号电极和位线之间的主导电路径以及由有源字线形成的栅电极。 由于字线和沟槽电容器之间的重叠，单元电池占据比现有技术单元电池更小的衬底面积。

    Method with improved controllability of a buried layer
    4.
    发明公开
    Method with improved controllability of a buried layer 有权
    Verfahren mit verbesserter Kontrollierbarkeit einer vergrabenen Schicht

    公开(公告)号：EP0948043A2

    公开(公告)日：1999-10-06

    申请号：EP99104721.8

    申请日：1999-03-10

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Bergner, Wolfgang ,  Alsmeier, Johann

    IPC分类号： H01L21/74

    CPC分类号： H01L27/10867

    摘要： Reduced variations in buried layer across the chip is provided. The reduction in variation is achieved by defining the top surface of the buried layer and then the lower surface of the buried layer. This results in improved control buried strap variations, thereby improving performance of the IC.

    摘要翻译： 提供了跨芯片的掩埋层的减小的变化。 通过限定掩埋层的顶表面，然后限定掩埋层的下表面来实现变化的减小。 这导致改进的控制掩埋带变化，从而提高IC的性能。

    Vertical transistor implemented in a memory cell comprising a trench capacitor
    5.
    发明公开
    Vertical transistor implemented in a memory cell comprising a trench capacitor 有权
    Vertikaler晶体管在einer Speicherzelle mit Grabenkondensator中实现

    公开(公告)号：EP0905783A1

    公开(公告)日：1999-03-31

    申请号：EP98115567.4

    申请日：1998-08-19

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A vertical transistor (258) used in a memory cell, such as a DRAM cell, having a trench capacitor (210). The vertical transistor (258) comprises a gate which includes a horizontal portion (253) and a vertical portion (245) located above the trench capacitor (210).

    摘要翻译： 在具有沟槽电容器（210）的诸如DRAM单元的存储单元中使用的垂直晶体管（258）。 垂直晶体管（258）包括一个栅极，该栅极包括位于沟槽电容器（210）上方的水平部分（253）和垂直部分（245）。

    Semiconductor device with vertical transistor and buried word line
    6.
    发明公开
    Semiconductor device with vertical transistor and buried word line 有权
    具有垂直晶体管的半导体器件和掩埋字线

    公开(公告)号：EP0948053A3

    公开(公告)日：2003-08-13

    申请号：EP99102355.7

    申请日：1999-02-06

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Rupp, Thomas ,  Alsmeier, Johann

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A word line (420) is buried beside a vertical semiconductor device (400). The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word line and the vertical transistor. In another embodiment, the vertical semiconductor device is a transistor having a vertically oriented gate. The word line is buried beside the vertically oriented gate, such that the topography of the word line is substantially planar.

    Shallow trench isolation for DRAM trench capacitor
    7.
    发明公开
    Shallow trench isolation for DRAM trench capacitor 失效
    浅沟槽隔离DRAM电容坟墓

    公开(公告)号：EP0908948A3

    公开(公告)日：2001-10-24

    申请号：EP98110953.1

    申请日：1998-06-16

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A random access memory cell having a trench capacitor formed below the surface of the substrate. A shallow trench isolation (455) is provided to isolate the memory cell from other memory cells of a memory array. The shallow trench isolation includes a top surface raised above the substrate wherein the amount that the top surface is raised is sufficient to prevent a divot (490) that is subsequently formed from extending below the substrate surface.