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    Improved integrated multi-layer test pads and methods therefor
    2.
    发明公开
    Improved integrated multi-layer test pads and methods therefor 失效
    Verbesserte integrierte Mehrschicht-Testflächenund Methodedafür

    公开(公告)号：EP0880173A2

    公开(公告)日：1998-11-25

    申请号：EP98304060.1

    申请日：1998-05-21

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Alswede, Frank ,  Mendelson, Ron ,  Davies, William ,  Prein, Frank ,  Hoyer, Ronald

    IPC分类号： H01L21/66 ,  H01L23/485

    CPC分类号： H01L22/32 ,  Y10S257/923

    摘要： A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3 X 3 block of the first pads.

    摘要翻译： 半导体晶片上的多层测试焊盘，其包括以行和列排列的互连的第一焊盘的下层矩阵。 多层测试垫包括设置在下面的矩阵之上并且在行和列之间的氧化物层。 多层测试垫还包括布置在氧化物层上方的互连的第二焊盘的上覆矩阵。 每个第二焊盘完全重叠至少九个第一焊盘，包括围绕九个第一焊盘的中心第一焊盘的四个氧化物区域。 第一个垫中的九个排列为第一个垫的3×3个块。