利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.016 秒)

    Method of manufacturing FET devices with maskless shallow trench isolation (STI)
    2.
    发明公开
    Method of manufacturing FET devices with maskless shallow trench isolation (STI) 失效
    Verfahren zur Herstellung von FET-Bauelementen mit flacher，maskenloser Grabenisolation

    公开(公告)号：EP0875927A2

    公开(公告)日：1998-11-04

    申请号：EP98303125.3

    申请日：1998-04-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Levy, Max Gerald ,  Fiegl, Bernhard ,  Glashauser, Walter ,  Prein, Frank

    IPC分类号： H01L21/762 ,  H01L21/8238

    CPC分类号： H01L21/76229

    摘要： FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.

    摘要翻译： FET器件（10）使用涂覆有衬垫（14）的半导体衬底（11）上的STI制造，在衬底（14）上形成凸起的有源硅器件区域和在掺杂硅衬底上由衬垫结构封装的虚拟有源硅台面（12） 垫结构。 在平台（12）上方具有保形突起，在器件（10）上沉积保形覆盖层氧化硅（22）层。 然后在覆层氧化硅层（22）上的多晶硅膜（24）上沉积有台面（12）之上的保形突起。 在CMP抛光步骤中去除多晶硅膜突起，其继续直到氧化硅层（22）暴露在焊盘结构（14）上。 接下来，在平台氧化硅层（12）上的保形二氧化硅层（22）的选择性RIE局部蚀刻，接着通过共形覆盖氧化硅层（22）的CMP平坦化，其将氧化硅层转换成平面氧化硅层 ，使用焊盘氮化硅（14）作为蚀刻停止。

    Improved integrated multi-layer test pads and methods therefor
    5.
    发明公开
    Improved integrated multi-layer test pads and methods therefor 失效
    Verbesserte integrierte Mehrschicht-Testflächenund Methodedafür

    公开(公告)号：EP0880173A2

    公开(公告)日：1998-11-25

    申请号：EP98304060.1

    申请日：1998-05-21

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Alswede, Frank ,  Mendelson, Ron ,  Davies, William ,  Prein, Frank ,  Hoyer, Ronald

    IPC分类号： H01L21/66 ,  H01L23/485

    CPC分类号： H01L22/32 ,  Y10S257/923

    摘要： A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3 X 3 block of the first pads.

    摘要翻译： 半导体晶片上的多层测试焊盘，其包括以行和列排列的互连的第一焊盘的下层矩阵。 多层测试垫包括设置在下面的矩阵之上并且在行和列之间的氧化物层。 多层测试垫还包括布置在氧化物层上方的互连的第二焊盘的上覆矩阵。 每个第二焊盘完全重叠至少九个第一焊盘，包括围绕九个第一焊盘的中心第一焊盘的四个氧化物区域。 第一个垫中的九个排列为第一个垫的3×3个块。

    Method of manufacturing FET devices with maskless shallow trench isolation (STI)
    9.
    发明公开
    Method of manufacturing FET devices with maskless shallow trench isolation (STI) 失效
    一种用于与平的，无掩模严重隔离FET器件的制备过程中

    公开(公告)号：EP0875927A3

    公开(公告)日：1999-07-07

    申请号：EP98303125.3

    申请日：1998-04-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Levy, Max Gerald ,  Fiegl, Bernhard ,  Glashauser, Walter ,  Prein, Frank

    IPC分类号： H01L21/762 ,  H01L21/8238

    CPC分类号： H01L21/76229

    摘要： FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.