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公开(公告)号：EP0901168A2
公开(公告)日：1999-03-10
申请号：EP98307178.8
申请日：1998-09-04
发明人： Hammerl, Erwin , Mandelman, Jack A. , Short, Alvin P. , Stengl, Reinhard J. , Ho, Herbert L. , Poschenrieder, Bernhard , Srinivasan, Radhika
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10832 , H01L27/10873
摘要： Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.
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公开(公告)号：EP0854510A3
公开(公告)日：1999-09-08
申请号：EP97310402.9
申请日：1997-12-22
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/31116
摘要： A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.
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3.发明公开Mask removal for etching a DRAM capacitor trench 失效Entfernung einer Maske beimGrabenätzeneines DRAM-Kondensators
公开(公告)号：EP0854510A2
公开(公告)日：1998-07-22
申请号：EP97310402.9
申请日：1997-12-22
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/31116
摘要： A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.
摘要翻译： 使用诸如反应离子蚀刻的各向异性技术来允许去除TEOS蚀刻掩模层的方法。 与湿式化学蚀刻技术相比，使用各向异性技术导致焊盘氧化物层的底切显着减少。 本发明的一个实施例涉及在焊盘TEOS层下方形成多晶硅蚀刻停止层。
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公开(公告)号：EP0844314A3
公开(公告)日：2001-04-11
申请号：EP97309500.3
申请日：1997-11-25
IPC分类号： C23F4/00 , H01L21/00 , C23C16/455
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45561
摘要： The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone. The mass flow controllers are utilized to ensure a uniform rate of chemical vapor deposition or etching across the surface of the substrate.
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公开(公告)号：EP0901168A3
公开(公告)日：2001-10-10
申请号：EP98307178.8
申请日：1998-09-04
发明人： Hammerl, Erwin , Mandelman, Jack A. , Short, Alvin P. , Stengl, Reinhard J. , Ho, Herbert L. , Poschenrieder, Bernhard , Srinivasan, Radhika
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10832 , H01L27/10873
摘要： A method for forming a trench capacitator dynamic random access memory comprising the steps of: providing a substrate (305) having a single crystalline structure and a substantially planar substrate surface, wherein the substrate surface comprises a pad layer having a substantially planar pad surface; fabricating a trench capacitor (315) in the substrate, wherein the trench capacitor comprises polysilicon; recessing the poly in the trench capacitor below the surface of the substrate to form a depression; forming an intermediate layer in the depression to a height above the pad surface, the intermediate layer having a single crystalline top plane (260); planarizing the intermediate layer and the pad surface such that the top plane of the intermediate layer is substantially planar with the substrate surface; and fabricating a transistor (370) on the top plane, wherein the active region of the second device is within the top plane.
摘要翻译： 公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。 在第一装置的上方形成具有单晶顶表面的层，以提供用于形成第二装置的有效区域的基座。
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公开(公告)号：EP0844314A2
公开(公告)日：1998-05-27
申请号：EP97309500.3
申请日：1997-11-25
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45561
摘要： The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone. The mass flow controllers are utilized to ensure a uniform rate of chemical vapor deposition or etching across the surface of the substrate.
摘要翻译： 本发明是一种用于在反应室内安装反应物气体的装置。 该装置能够用于气相沉积和蚀刻工艺中。 该装置基本上补偿由气体耗尽引起的晶片边缘处的气相沉积和蚀刻不均匀的问题。 具有延伸穿过其中的多个孔的气体分配板附接到反应室的内表面。 至少一个真空密封隔板设置在气体分配板的表面和室的内表面之间。 隔板将板和反应室之间的空间分隔成气体分配区。 气体入口连接到每个气体分配区。 每个气体入口管线具有至少一个质量流量控制器，其调节到每个气体分配区域的气体流量。 质量流量控制器用于确保跨越基板表面的化学气相沉积或蚀刻的均匀速率。
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公开(公告)号：EP0844314B1
公开(公告)日：2004-02-11
申请号：EP97309500.3
申请日：1997-11-25
IPC分类号： C23F4/00 , H01L21/00 , C23C16/455
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45561
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8.发明公开Method of forming self-aligned contact holes using a sacrificial polysilicon layer 失效一种用于生产使用多晶硅的辅助层自对准接触孔的方法
公开(公告)号：EP0766301A2
公开(公告)日：1997-04-02
申请号：EP96113456.6
申请日：1996-08-21
IPC分类号： H01L21/768
CPC分类号： H01L21/28
摘要： A method of forming a self-aligned contact hole, in particular a bitline contact, includes steps of first depositing a sacrificial polysilicon layer (4) on a spacer dielectric film (3), and thereafter patterning the polysilicon. The polysilicon layer is a sacrificial fill-in for a bitline contact stud. The method further includes depositing a middle-of-line (MOL) oxide (6) on the polysilicon layer (4), and planarizing the MOL oxide by chemical-mechanical polishing (CMP). Thereafter, the polysilicon layer (4) is etched away and the spacer dielectric film (3) is etched to form a self-aligned bitline contact.
摘要翻译： 形成自对准接触孔，特别是位线接触，所述的方法包括首先沉积上的间隔物的电介质薄膜 - （3）牺牲多晶硅层（4），并且之后图案化该多晶硅的步骤。 多晶硅层是牺牲填充在为位线接触柱。 该方法包括另外的多晶硅层（4）上沉积中间的线（MOL）氧化物（6），并通过化学机械抛光（CMP）的MOL氧化物平坦化。 那里后，多晶硅层（4）被蚀刻掉和间隔电介质成膜（3）进行蚀刻，以形成自对准的位线接触。
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9.发明公开Method of forming self-aligned contact holes using a sacrificial polysilicon layer 失效一种用于生产使用多晶硅的辅助层自对准接触孔的方法
公开(公告)号：EP0766301A3
公开(公告)日：1998-04-15
申请号：EP96113456.6
申请日：1996-08-21
IPC分类号： H01L21/768
CPC分类号： H01L21/28
摘要： A method of forming a self-aligned contact hole, in particular a bitline contact, includes steps of first depositing a sacrificial polysilicon layer (4) on a spacer dielectric film (3), and thereafter patterning the polysilicon. The polysilicon layer is a sacrificial fill-in for a bitline contact stud. The method further includes depositing a middle-of-line (MOL) oxide (6) on the polysilicon layer (4), and planarizing the MOL oxide by chemical-mechanical polishing (CMP). Thereafter, the polysilicon layer (4) is etched away and the spacer dielectric film (3) is etched to form a self-aligned bitline contact.
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