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    Method of connecting a dram trench capacitor
    2.
    发明公开
    Method of connecting a dram trench capacitor 失效
    KontaktierverfahrenfürDRAM-Grabenkondensator

    公开(公告)号：EP0791959A1

    公开(公告)日：1997-08-27

    申请号：EP97102361.9

    申请日：1997-02-13

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Stengl, Reinhard J. ,  Hammerl, Erwin ,  Mandelman, Jack A. ,  Ho, Herbert L. ,  Srinivasan, Radhika ,  Short, Alvin P.

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832

    摘要： In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

    摘要翻译： 在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，电连接（90）通过有选择地控制在沟槽中存在的N型或P型掺杂剂的扩散扩散形成 通过从沟槽侧壁外延（epi）生长的单晶半导体材料（60）。 这种外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

    DRAM cell with trench capacitor
    3.
    发明公开
    DRAM cell with trench capacitor 审中-公开
    DRAM-Zelle mit Grabenkondensator

    公开(公告)号：EP0901168A3

    公开(公告)日：2001-10-10

    申请号：EP98307178.8

    申请日：1998-09-04

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Hammerl, Erwin ,  Mandelman, Jack A. ,  Short, Alvin P. ,  Stengl, Reinhard J. ,  Ho, Herbert L. ,  Poschenrieder, Bernhard ,  Srinivasan, Radhika

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L27/10873

    摘要： A method for forming a trench capacitator dynamic random access memory comprising the steps of: providing a substrate (305) having a single crystalline structure and a substantially planar substrate surface, wherein the substrate surface comprises a pad layer having a substantially planar pad surface; fabricating a trench capacitor (315) in the substrate, wherein the trench capacitor comprises polysilicon; recessing the poly in the trench capacitor below the surface of the substrate to form a depression; forming an intermediate layer in the depression to a height above the pad surface, the intermediate layer having a single crystalline top plane (260); planarizing the intermediate layer and the pad surface such that the top plane of the intermediate layer is substantially planar with the substrate surface; and fabricating a transistor (370) on the top plane, wherein the active region of the second device is within the top plane.

    摘要翻译： 公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。 在第一装置的上方形成具有单晶顶表面的层，以提供用于形成第二装置的有效区域的基座。