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    Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications
    2.
    发明公开
    Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications 有权
    隔离栅栏Flachen Grabens（STI）fürVLSI-Anwendungen

    公开(公告)号：EP1026734A2

    公开(公告)日：2000-08-09

    申请号：EP00101726.8

    申请日：2000-01-27

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Ho, Herbert ,  Srinivasan, Radhika ,  Hammerl, Erwin ,  Agahi, Farid ,  Bronner, Gary ,  Flietner, Bertrand

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.

    摘要翻译： 公开了浅沟槽隔离通孔的寄生泄漏的减少，其中通过在沉积氮化硅衬垫之前沉积绝缘氧化物层来增加氮化硅衬垫和有源硅侧壁之间的距离。 优选地，绝缘氧化物层包括原硅酸四乙酯。 该方法包括：将一个或多个浅沟槽隔离件蚀刻成半导体晶片; 将绝缘氧化物层沉积到沟槽中; 在沟槽中生长热氧化物; 以及在沟槽中沉积氮化硅衬垫。 可以在沉积绝缘氧化物层之前或之后生长热氧化物。

    Method of connecting a dram trench capacitor
    7.
    发明公开
    Method of connecting a dram trench capacitor 失效
    KontaktierverfahrenfürDRAM-Grabenkondensator

    公开(公告)号：EP0791959A1

    公开(公告)日：1997-08-27

    申请号：EP97102361.9

    申请日：1997-02-13

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Stengl, Reinhard J. ,  Hammerl, Erwin ,  Mandelman, Jack A. ,  Ho, Herbert L. ,  Srinivasan, Radhika ,  Short, Alvin P.

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832

    摘要： In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

    摘要翻译： 在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，电连接（90）通过有选择地控制在沟槽中存在的N型或P型掺杂剂的扩散扩散形成 通过从沟槽侧壁外延（epi）生长的单晶半导体材料（60）。 这种外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

    Shallow trench isolation with thin nitride liner
    8.
    发明公开
    Shallow trench isolation with thin nitride liner 失效
    用薄的氮化物衬垫进行浅沟槽隔离

    公开(公告)号：EP0690493A2

    公开(公告)日：1996-01-03

    申请号：EP95480072.8

    申请日：1995-06-09

    申请人： International Business Machines Corporation

    发明人： Fahey, Paul Martin ,  Morikado, Mutsuo ,  Hammerl, Erwin ,  Ho, Herbert Lei

    IPC分类号： H01L21/76

    CPC分类号： H01L21/3105 ,  H01L21/76232 ,  Y10S148/05

    摘要： A method of forming shallow trench isolation with a nitride liner layer for devices in integrated circuits solves a problem of recessing the nitride liner that led to unacceptable voids in the trench filler material by using a liner thickness of less than 5nm. A densification step of a pyrogenic oxide anneal at 800°C not only drives out impurities and achieves the same density as a conventional argon anneal at 1000°C, but also drastically reduces the thermal load. Trenches (50) are formed as standard in a silicon substrate (10) using a conventional SiO₂ /Si₃N₄ passivation layer (20/30). Then a thin layer (52) of thermal oxide is provided on the trench sidewalls. Fig. 2 illustrates the results of a step according to a thin layer (32) of LPCVD nitride is deposited at a pressure of 200 mTorr with a flow of NH₃:SiH₂C1₂ 10:1 for 2 minutes at 770°C. This layer has been discovered to be immune to the recessing problem.
    An oxide liner (60) made of TEOS SiO₂ is then deposited. The structure is annealed and the TEOS SiO₂ is classified. Finally the structure is planarized and the passivation layer removed. As apparent from the drawings, there is no longer any recess in the LPCVD nitride layer.

    摘要翻译： 使用氮化物衬垫层形成用于集成电路中的器件的浅沟槽隔离的方法解决了通过使用小于5nm的衬垫厚度来凹陷导致沟槽填充材料中的不可接受的空隙的氮化物衬垫的问题。 800℃热解氧化退火的致密化步骤不仅驱出杂质，并且达到与1000℃下的传统氩气退火相同的密度，而且大大降低了热负荷。 使用传统的SiO 2 / Si 3 N 4钝化层（20/30）在硅衬底（10）中形成标准沟槽（50）。 然后在沟槽侧壁上提供热氧化物薄层（52）。 图2示出了根据LPCVD氮化物薄层（32）的步骤的结果，在700毫托的压力和770℃的NH 3 :SiH 2 Cl 2的流量为10：1的条件下沉积2分钟。 已经发现这一层不受隐性问题的影响。 然后沉积由TEOS SiO 2制成的氧化物衬垫（60）。 该结构被退火并且TEOS SiO 2被分类。 最后，该结构被平面化并去除钝化层。 从附图中可以看出，在LPCVD氮化物层中不再有凹陷。

    DRAM cell with trench capacitor
    10.
    发明公开
    DRAM cell with trench capacitor 审中-公开
    DRAM-Zelle mit Grabenkondensator

    公开(公告)号：EP0901168A3

    公开(公告)日：2001-10-10

    申请号：EP98307178.8

    申请日：1998-09-04

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Hammerl, Erwin ,  Mandelman, Jack A. ,  Short, Alvin P. ,  Stengl, Reinhard J. ,  Ho, Herbert L. ,  Poschenrieder, Bernhard ,  Srinivasan, Radhika

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L27/10873

    摘要： A method for forming a trench capacitator dynamic random access memory comprising the steps of: providing a substrate (305) having a single crystalline structure and a substantially planar substrate surface, wherein the substrate surface comprises a pad layer having a substantially planar pad surface; fabricating a trench capacitor (315) in the substrate, wherein the trench capacitor comprises polysilicon; recessing the poly in the trench capacitor below the surface of the substrate to form a depression; forming an intermediate layer in the depression to a height above the pad surface, the intermediate layer having a single crystalline top plane (260); planarizing the intermediate layer and the pad surface such that the top plane of the intermediate layer is substantially planar with the substrate surface; and fabricating a transistor (370) on the top plane, wherein the active region of the second device is within the top plane.

    摘要翻译： 公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。 在第一装置的上方形成具有单晶顶表面的层，以提供用于形成第二装置的有效区域的基座。