摘要:
A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.
摘要:
An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.