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1.发明公开METHOD AND CIRCUIT FOR SYNCHRONIZING PHASE OF VIDEO SIGNAL, AND COMBINING DEVICE 失效方法与电路的相位同步视频信号和组合装置
公开(公告)号：EP0767590A4
公开(公告)日：2000-11-29
申请号：EP96910206
申请日：1996-04-19
申请人： SONY CORP
发明人： YAMAUCHI ETSURO , MOGI YASUHIDE , FUKUDA TOKUYA
摘要： Continuous wave signals synchronized with first chrominance subcarrier signals are generated (by means of a chrominance subcarrier extracting circuit (2), a phase error detecting circuit (3), an A/D conversion circuit (4), and a digital oscillation circuit (5)) from the analog video signals including the first chrominance subcarrier signals supplied to an input terminal (1). Digital video signals including chrominance components supplied to an input terminal (7) is converted into a composite video signal including chrominance signals (by means of a digital video signal converting circuit (6)). In this case, the chrominance components are converted into the chrominance signals by using the continuous wave signals, and the phase of the first chrominance subcarrier signals of the analog video signals is synchronized with that of the second chrominance subcarrier signals of the chrominance signals of the composite video signal produced from the digital video signals. Thus, the phase of the chrominance signals of the analog video signals can be synchronized with that of the chrominance signals of the composite video signal produced from the digital video signal, with, for example, a simple circuit constitution, and a picture drawn by the digital video signals can be easily combined with another picture drawn by the analog video signals.
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公开(公告)号：EP0779713A4
公开(公告)日：1998-07-22
申请号：EP96910207
申请日：1996-04-19
申请人： SONY CORP
发明人： MOGI YASUHIDE , YAMAUCHI ETSURO
CPC分类号： H04N5/073 , H03L7/085 , H03L7/093 , H03L7/0991 , H03L7/0994 , H04N5/0736 , H04N9/45
摘要： Signals (digital sine wave signals) (Sd) stored in a memory means (3) are read. The phase of input signal (analog sine wave signal) (Sr) supplied to an input terminal is compared with that of signal (Sa) generated by D/A-converting the signals (Sd) (by means of a comparator (2)), the reading address signal of the memory means (3) is controlled based on the phase error signal (a) generated as a result of the comparison by the comparator (2) (by means of an address forming circuit (5)). Thus, the phase of the digital sine wave signals (Sd) supplied to an output terminal (6) is synchronized with that of the analog sine wave signals (Sr) supplied to the input terminal (1). Desired digital signals synchronized with the phase of the input signals can be generated by processing the digital signals with a simple constitution.
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