摘要:
The present disclosure relates to an electronic analog-to-digital conversion device (100) which comprises: - an analog-to-digital conversion block (101) having a first input (1) for receiving a voltage signal (Vout) to be converted on the basis of a reference voltage signal (V REF ) provided to a second input (2) of the same analog-to-digital conversion block (101); - an input block (102) having an input terminal (3) and an output terminal (4) connected to the first input (1) of the analog-to-digital conversion block (101). The input block (102) is arranged for processing an input voltage signal (Vin) applied to the input terminal (3) to generate the voltage signal (Vout) at the output terminal (4). The input block (102) comprises: - a first resistive network (103) operatively connected to both the input terminal (3) and the output terminal (4); - a second resistive network (104) connected between the output terminal (4) and a reference potential (GND). The input block (102) is characterized by comprising an active network (105) connected between an output node (5) of the first resistive network (103) and the output terminal (4). The active network (105) has a first input terminal (6) directly connected to the second input (2) of the analog-to-digital conversion block (101) for receiving the same reference voltage signal (V REF ) provided to the second input (2) so that the input voltage signal (Vin) is processed by the input block (102) on the basis of such reference voltage signal (V REF ).
摘要:
A method (100) of SAR - Successive Approximation Register - analog to digital conversion is disclosed. The method is such to perform N+1 SAR cycles for obtaining an output digital code having N bits. The method (100) comprises a step of receiving and sampling (101) an analog signal (V in ). After the execution of the first N-1 SAR cycles, the method (100) comprises the steps of: - performing (105) the N th SAR cycle by setting (106) a N th tentative analog signal corresponding to a provisional digital code (X P ) and comparing (107) the N th tentative analog signal with the sampled analog signal thus obtaining a N th comparison result; - performing (108) the (N+1) th SAR cycle by setting (109) a (N+1) th tentative analog signal on the basis of the N th comparison result, comparing (110) the (N+1) th tentative analog signal with the sampled analog signal thus obtaining a second comparison result and correcting (111) the provisional digital code (X P ) on the basis of the (N+1) th comparison result for obtaining the output digital code (X c ). Each of the comparisons is performed is such a way that the N th and (N+1) th SAR cycles comprise a plurality sub-comparisons in such a way that at the end of each of said cycles a set of sub-results is obtained. The last two comparison results are obtained taking into account the corresponding set of sub-results.