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    Electronic device with body-biasing circuit for portable equipment with USB connector for headset
    3.
    发明公开
    Electronic device with body-biasing circuit for portable equipment with USB connector for headset 有权
    与Körpervormagnetisierungsschaltung一种电子装置，用于与USB端口，用于耳机的便携式设备

    公开(公告)号：EP2568606A1

    公开(公告)日：2013-03-13

    申请号：EP11180174.2

    申请日：2011-09-06

    申请人： ST-Ericsson SA

    发明人： Nicollini, Germano ,  Zamprogno, Marco

    IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03F3/185

    CPC分类号： H03K17/6871 ,  H03F1/52 ,  H03F3/185 ,  H03F3/301

    摘要： The invention relates to an electronic device (101) comprising:
    - a electrical portion (102) arranged to operate at a first reference voltage (VUSB) and at a second reference voltage (VCCHS), the electrical portion (102) comprising:
    - a digital data transmission stage (103) having at least a first output terminal (03) to provide a first digital signal (D1) having a voltage value corresponding to the first reference voltage (VUSB) or to a further reference voltage (GND);
    - a audio signal amplification stage (104) comprising at least an amplifier (105) having an output stage (106) comprising a PMOS transistor (MP) and a NMOS transistor (MN) connected in series one another between said second reference voltage (VCCHS) and a further reference voltage (VSSHS), said output stage (106) having a respective output terminal (05) connected to said at least first output terminal (03) of the digital data transmission stage (103) to provide an output signal (OUT), said output signal (OUT) corresponding to said first digital signal (D1) in a digital data transmission mode of the electrical portion (102) or to an audio signal (HSL) in an audio amplification mode of the electrical portion (102);
    - at least one biasing circuit (107) of the body terminal (B) of the PMOS transistor (MP) of said output stage (106).
    The electronic device (101) is characterized in that the at least one biasing circuit (107) is arranged to supply to the body terminal (B) of the PMOS transistor (MP) of the output stage (106) a biasing voltage (VbMP) corresponding to the highest between the voltage value of the output signal (OUT) and the second reference voltage (VCCHS) of the electrical portion (102) of the electronic device (101).

    摘要翻译： 本发明涉及到电子装置（101），包括： - 设置在第一参考电压（VUSB）和在第二参考电压（VCCHS），包括电气部分（102）进行操作的电气部分（102）： - 一 具有至少一个第一输出端子（03），以提供具有一个电压值对应于第一参考电压（VUSB）或到参考电压此外（GND）的第一数字信号（D1）的数字数据传输阶段（103）; - 在包括串联连接的一个另一个所述第二参考电压之间的PMOS晶体管（MP）和NMOS晶体管（MN）的输出级（106），其具有（VCCHS一个音频信号放大级（104）在放大器至少包括：（105） ）和另一参考电压（VSSHS），所述输出级（106），其具有在数字数据传输阶段（103的至少第一输出端（03）连接到所述一个respectivement输出端子（05）），以提供给输出信号（ OUT），所述输出信号（OUT）在在电部分的音频放大模式的音频信号（HSL）对应于所述第一数字信号（D1）（在电部分102的数字数据传输模式），或（102 ）; - 所述输出级（106）的PMOS晶体管（MP）的体端子（B）的至少一个偏置电路（107）。 所述的电子设备（101）在DASS模具的特征在于，至少一个偏置电路（107）被布置成提供给PMOS晶体管输出级（106）的偏置电压的（MP）的体端子（B）（VbMP） 对应于输出信号（OUT）和电子设备（101）的电气部分（102）的第二参考电压（VCCHS）的电压值之间的最高的。

    Single-ended to differential buffer circuit and method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs
    5.
    发明公开
    Single-ended to differential buffer circuit and method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs 有权
    缓冲电路与施加到单个输入模拟信号到接收电路具有差动输入的单个输入，差分输出和方法，用于至少一个电压的耦合，

    公开(公告)号：EP2437268A1

    公开(公告)日：2012-04-04

    申请号：EP10183195.6

    申请日：2010-09-30

    申请人： ST-Ericsson SA

    发明人： Nicollini, Germano ,  Minuti, Alberto ,  Zamprogno, Marco

    IPC分类号： G11C27/02 ,  H03F3/45 ,  H03M1/12 ,  H03M3/02

    CPC分类号： H03M1/124 ,  G11C27/026 ,  H03F3/45475 ,  H03F3/45986 ,  H03F2203/45512 ,  H03F2203/45536

    摘要： A single-ended to differential buffer circuit is (21,22) is disclosed, adapted to couple at least an input analog signal (Vin) to a receiving circuit (24).
    The buffer circuit (21,22) comprises an output section (22) comprising a differential amplifier (25) having a first (31) and a second (32) input, a first (41) and a second (42) output.
    The buffer circuit further comprises an input section (21) comprising a first (CS1) and a second (CS2) switched capacitor, each adapted to sample said input analog signal (Vin) and having a first side (p1',p2') and a second side (p1", p2"), the first sides (p1', p2') of the first and second switched capacitors being controllably connectable / disconnectable to/from said first (41) and second (42) outputs respectively.
    In the buffer circuit the second sides (p1",p2") of said first (CS1) and second (CS2) switched capacitors are controllably connectable/disconnectable to/from said first (31) and second (32) inputs of the differential amplifier (25) respectively.
    Moreover, in the buffer circuit the second sides (p1", p2") of the first and second switched capacitors (CS1,CS2) are controllably connectable/disconnectable to/from said second output (42) and said first output (41) respectively.
    A method (100) for coupling at least a single-ended input analog signal (V in ) to a receiving circuit (24) with differential inputs is also disclosed.

    摘要翻译： 单端到差分缓冲电路是（21,22）是圆盘游离缺失，适于耦接至少输入模拟信号（Vin）到接收电路（24）。 缓冲电路（21,22）包括到输出部分（22）包括具有第一（31）的差分放大器（25）和第二（32）输入端，第一（41）和第二（42）输出。 包括第一（CS1）和第二（CS2）的缓冲电路的输入部分的步骤还包括（21）的开关电容器，每个angepasst采样所述输入模拟信号（Vin）和具有第一侧（P1”，P2' ）和 的第二侧上的第一和第二组（P1“P2”），所述第一侧部（P1”，P2' ）开关电容器是可控地可连接/可分离的向/从所述第一（41）和第二（42）分别输出。 在缓冲电路的第二侧所述第一（CS1）和第二（CS2）的（P1“P2”）开关电容器是可控地可连接的/可断开的从所述第一（31）和所述差分放大器的第二（32）输入到/ （25）分别。 更完了，在缓冲电路中的第二侧上的第一和第二组（P1“P2”）开关电容器（CS1，CS2）是可控地可连接/可分离的向/从所述第二输出（42）和分别在第一输出（41）所述 ， 一种用于将至少一个单端输入模拟信号的方法（100）（以V）至游离缺失的接收电路（24）与差分输入gibt光盘。

    Circuit protection
    7.
    发明公开
    Circuit protection 有权
    电路保护

    公开(公告)号：EP2461457A1

    公开(公告)日：2012-06-06

    申请号：EP10425368.7

    申请日：2010-12-02

    申请人： ST-Ericsson SA

    发明人： Zamprogno, Marco ,  Minuti, Alberto ,  Nicollini, Germano

    IPC分类号： H02J7/00 ,  H02H3/20

    CPC分类号： H02H3/20 ,  H02H3/207 ,  H02J1/10 ,  H02J7/0031 ,  H02J7/345

    摘要： An apparatus (100) for protecting a circuit (200) from an input voltage comprises a switchable element (10) arranged to couple the input voltage (V IN ) to the circuit (200) in response to a first control signal (DRV1) having a first value and to decouple the input voltage (V IN ) from the circuit (200) in response to the first control signal (DRV1) having a second value. A monitor stage (20) compares a monitored voltage (V MON ) to a threshold (V TH ). A controller (30) provides the first control signal (DRV1) to the switchable element (10), the first control signal (DRV1) having the first value when the monitored voltage (V MON ) is on one side of the threshold (V TH ) and the second value when the monitored voltage (V MON ) is on the other side of the threshold (V TH ), wherein the first value is independent of the input voltage (V IN ) and the second value is equal to the input voltage (V IN ).

    Analog-to-digital conversion device
    8.
    发明公开
    Analog-to-digital conversion device 审中-公开
    模拟数字-Wandlersystem

    公开(公告)号：EP2690788A1

    公开(公告)日：2014-01-29

    申请号：EP12178324.5

    申请日：2012-07-27

    申请人： ST-Ericsson SA

    发明人： Minuti, Alberto ,  Girardi, Francesca ,  Nicollini, Germano ,  Zamprogno, Marco

    IPC分类号： H03M1/12

    CPC分类号： H03M1/12 ,  H02J7/00 ,  H03M1/129

    摘要： The present disclosure relates to an electronic analog-to-digital conversion device (100) which comprises:
    - an analog-to-digital conversion block (101) having a first input (1) for receiving a voltage signal (Vout) to be converted on the basis of a reference voltage signal (V REF ) provided to a second input (2) of the same analog-to-digital conversion block (101);
    - an input block (102) having an input terminal (3) and an output terminal (4) connected to the first input (1) of the analog-to-digital conversion block (101).
    The input block (102) is arranged for processing an input voltage signal (Vin) applied to the input terminal (3) to generate the voltage signal (Vout) at the output terminal (4). The input block (102) comprises:
    - a first resistive network (103) operatively connected to both the input terminal (3) and the output terminal (4);
    - a second resistive network (104) connected between the output terminal (4) and a reference potential (GND).
    The input block (102) is characterized by comprising an active network (105) connected between an output node (5) of the first resistive network (103) and the output terminal (4). The active network (105) has a first input terminal (6) directly connected to the second input (2) of the analog-to-digital conversion block (101) for receiving the same reference voltage signal (V REF ) provided to the second input (2) so that the input voltage signal (Vin) is processed by the input block (102) on the basis of such reference voltage signal (V REF ).

    摘要翻译： 本公开涉及一种电子模数转换装置（100），其包括： - 模数转换块（101），具有用于接收要转换的电压信号（Vout）的第一输入（1） 基于提供给同一模数转换块（101）的第二输入（2）的参考电压信号（V REF）; - 具有连接到模数转换块（101）的第一输入（1）的输入端（3）和输出端（4）的输入块（102）。 输入块（102）被布置用于处理施加到输入端子（3）的输入电压信号（Vin），以在输出端子（4）产生电压信号（Vout）。 输入块（102）包括： - 可操作地连接到输入端（3）和输出端（4）的第一电阻网络（103）。 - 连接在输出端（4）和参考电位（GND）之间的第二电阻网络（104）。 输入块（102）的特征在于包括连接在第一电阻网络（103）的输出节点（5）和输出端（4）之间的有源网络（105）。 有源网络（105）具有直接连接到模拟 - 数字转换块（101）的第二输入（2）的第一输入端（6），用于接收与第二输入端相连的第二输入端 输入（2），使得输入电压信号（Vin）由输入块（102）基于这样的参考电压信号（V REF）来处理。

    Method of successive approximation A/D conversion
    9.
    发明公开
    Method of successive approximation A/D conversion 审中-公开
    Verfahren zur A / D-Umwandlung mit sukzessiverAnnäherung

    公开(公告)号：EP2600530A1

    公开(公告)日：2013-06-05

    申请号：EP11191807.4

    申请日：2011-12-02

    申请人： ST-Ericsson SA

    发明人： Zamprogno, Marco ,  Girardi, Francesca ,  Minuti, Alberto

    IPC分类号： H03M1/06 ,  H03M1/42

    CPC分类号： H03M1/466 ,  H03M1/0697 ,  H03M1/0845 ,  H03M1/42 ,  H03M1/46

    摘要： A method (100) of SAR - Successive Approximation Register - analog to digital conversion is disclosed. The method is such to perform N+1 SAR cycles for obtaining an output digital code having N bits. The method (100) comprises a step of receiving and sampling (101) an analog signal (V in ).
    After the execution of the first N-1 SAR cycles, the method (100) comprises the steps of:
    - performing (105) the N th SAR cycle by setting (106) a N th tentative analog signal corresponding to a provisional digital code (X P ) and comparing (107) the N th tentative analog signal with the sampled analog signal thus obtaining a N th comparison result;
    - performing (108) the (N+1) th SAR cycle by setting (109) a (N+1) th tentative analog signal on the basis of the N th comparison result, comparing (110) the (N+1) th tentative analog signal with the sampled analog signal thus obtaining a second comparison result and correcting (111) the provisional digital code (X P ) on the basis of the (N+1) th comparison result for obtaining the output digital code (X c ).
    Each of the comparisons is performed is such a way that the N th and (N+1) th SAR cycles comprise a plurality sub-comparisons in such a way that at the end of each of said cycles a set of sub-results is obtained. The last two comparison results are obtained taking into account the corresponding set of sub-results.

    摘要翻译： 公开了SAR - 逐次近似寄存器的方法（100） - 模数转换。 该方法是执行N + 1个SAR周期以获得具有N位的输出数字码。 方法（100）包括接收和采样（101）模拟信号（V in）的步骤。 在执行第一N-1个SAR周期之后，方法（100）包括以下步骤： - 通过设置（106）对应于临时数字码的第N个暂时模拟信号（105）来执行（105）第N个SAR周期 XP），并将第N个暂定模拟信号与采样的模拟信号进行比较（107），从而获得第N个比较结果; 根据第N个比较结果，设置（109）第（N + 1）个暂定模拟信号，执行（108）第（N + 1）个SAR周期，比较（110）第（N + 1） 从而获得第二比较结果并且基于用于获得输出数字码（X c）的第（N + 1）比较结果来校正（111）临时数字码（XP）（111）。 执行每个比较是使得第N和第（N + 1）个SAR周期包括多个子比较，使得在每个所述周期的结尾处获得一组子结果 。 考虑到相应的一组子结果，获得最后两个比较结果。