-
公开(公告)号：EP4439986A1
公开(公告)日：2024-10-02
申请号：EP24166374.9
申请日：2024-03-26
发明人： Liu, Yong , Zhang, Wei , Cao, Jun
CPC分类号： H03M1/0641 , H03M1/46
摘要： A system includes a dither generator module that includes a most significant bits (MSB) dither generator device that generates a first random value. The dither generator module also includes a least significant bits (LSB) dither generator device that generates a second random value. The system further includes a first digital to analog converter (DAC) that receives a sum of the first random value and the second random value and generates a dither signal based on the sum of the first random value and the second random value. The system also includes an analog to digital converter (ADC) that receives a sum of the dither signal and a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to produce a digitized output signal.
-
2.发明公开
公开(公告)号：EP4385016A1
公开(公告)日：2024-06-19
申请号：EP21824157.8
申请日：2021-11-13
发明人： TRAN, Hieu Van
IPC分类号： G11C7/10 , G11C11/00 , G11C11/56 , G11C27/00 , G11C11/54 , G06N3/063 , G11C7/16 , H03M1/46 , H03M1/74
CPC分类号： G11C7/1006 , G11C11/005 , G11C11/5642 , G11C11/5628 , G11C27/005 , G11C11/54 , G11C7/16 , H03M1/46 , H03M1/742 , G06N3/065 , G06N3/0464 , G06N3/0442
-
公开(公告)号：EP3417546A1
公开(公告)日：2018-12-26
申请号：EP17705109.1
申请日：2017-02-14
发明人： LIU, Yuhang , AXMON, Joakim , BRESCHEL, Michael , HILL, Johan
CPC分类号： H03M1/0624 , H03L7/0996 , H03M1/1255 , H03M1/46 , H04B1/16 , H04B1/40 , H04L27/2689
摘要： Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.
-
公开(公告)号：EP3139186B1
公开(公告)日：2018-08-01
申请号：EP15183285.4
申请日：2015-09-01
申请人： NXP B.V.
发明人： SCHAPENDONK, Edwin
摘要： The disclosure relates to sensor systems, in particular to such systems incorporating analogue to digital converters, for example for use in providing a digital signal derived from sensing elements connected in a bridge configuration. Example embodiments include a sensor circuit (300) comprising: first and second paths (301 a, 301 b) comprising respective first and second sensing elements (R1 a, R2a) connected between first and second supply lines (302a, 302b); an analogue to digital converter (304, 305, 306) having a differential input connected to receive a differential voltage signal (Vinp-Vinn) between the first and second sensing elements (R1 a, R2a) and an output for providing a digital output signal (Dout) representing a difference between the first and second sensing elements (R1 a, R2a), the analogue to digital converter comprising: a plurality of current sources (311 0 ...311 n ) connected between the first and second supply lines (302a, 302b), each current source being switchably connected to either the first or second sensing elements (R1 a, R2a); and control logic (306) configured to selectively switch current from each of the current sources (311 0 ...311 n ) to either the first path (301 a) or the second path (301 b) in dependence on the differential voltage signal (Vinp-Vinn).
-
公开(公告)号：EP3334049A1
公开(公告)日：2018-06-13
申请号：EP16202932.6
申请日：2016-12-08
发明人： DING, Ming , LI, Hanyue , HARPE, Pieter
CPC分类号： H03M1/1023 , H03M1/0675 , H03M1/1033 , H03M1/1047 , H03M1/108 , H03M1/44 , H03M1/46 , H03M1/462 , H03M1/468
摘要： A method of DAC mismatch calibration in a SAR ADC (600) comprising the steps of: determining a number of bits of an analog input signal (V IN ); detecting if a binary code determined from the analog input signal (V IN ) matches at least one trigger code; using at least one setting code to determine a calibration residue signal (V* RES ) and a calibration bit (B* LSB ); analyzing a least significant bit of the digital signal (C OUT ) and the calibration bit (B* LSB ); determining an indication of a presence of DAC mismatch; and calibrating the DAC mismatch. As the determination of the calibration bit (B* LSB ) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.
-
公开(公告)号：EP3192153A2
公开(公告)日：2017-07-19
申请号：EP15818933.2
申请日：2015-07-10
发明人： KUHN, Ruediger , GERBER, Johannes , RUCK, Bernhard , QAIYUM, Asif
IPC分类号： H02K5/22
CPC分类号： G01R19/16576 , H03M1/1245 , H03M1/46
摘要： A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin|
摘要翻译： 双比较器电路包括主比较器，其提供包括主MOS差分对的第一判定输出（外部）和包括提供第二判定输出（外部）的辅助MOS差分对的辅助比较器。 辅助比较器接收差分输入电压（Vin），并且产生耦合到主比较器的使能输入的控制信号。 当| Vin | <预定电压电平（PVL）时，执行第一操作模式（OM），其中控制信号激活主比较器。 当主差分对由开关保护以防止发生瞬态电压输入偏移（VIO）时，| Vin |≥PVL时实现第二个OM。 逻辑电路具有接收输出端和外部输入端的逻辑输入，以及在第一OM中使用outmain并在第二OM中使用outaux时为双比较器电路提供判定结果的逻辑输出。
-
公开(公告)号：EP3188368A1
公开(公告)日：2017-07-05
申请号：EP16204137.0
申请日：2016-12-14
申请人： Analog Devices, Inc.
CPC分类号： H03M1/1071 , H03M1/1038 , H03M1/16 , H03M1/38 , H03M1/46 , H03M3/412 , H03M3/464
摘要： For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.
摘要翻译： 对于利用反馈数模转换器（DAC）进行转换的模数转换器（ADC），最终的模拟输出会受到反馈DAC误差的影响或失真。 可以实施数字测量技术来确定连续时间Δ-Σ调制器（CTDSM）中的反馈DAC或连续时间流水线调制器中的时序失配误差。 该方法利用输出到整个调制器输出的每个DAC单元元件（UE）的互相关来分别测量其时序失配误差。 具体而言，使用基于互相关函数中的下一个抽头的峰值和值的比率来估计定时不匹配误差。 获得的错误可以存储在查找表中，并在数字域或模拟域中完全纠正。
-
8.发明公开METHOD AND APPARATUS FOR CLOSED LOOP CONTROL OF SUPPLY AND/OR COMPARATOR COMMON MODE VOLTAGE IN A SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER 有权方法和设备，用于控制闭合回路供电和/或比较器共模电压数模转换器与逐次逼近寄存器中
公开(公告)号：EP2962395A1
公开(公告)日：2016-01-06
申请号：EP14710128.1
申请日：2014-02-21
CPC分类号： H03M1/0604 , G06F1/3296 , H03M1/00 , H03M1/46 , Y02D10/172
摘要： A method and apparatus for controlling supply voltage for a successive approximation register analog to digital converter and comparator common mode voltage. The method comprises: measuring a successive approximation register conversion time; comparing the successive approximation register conversion time with a desired conversion time; and if necessary, performing a closed loop adjustment of at least one of the supply and/or comparator common mode voltage. The apparatus consists of a common mode voltage and regulator correction module. The common mode voltage and regulator correction module includes a phase frequency detector, a charge pump and may include a transconductance cell.
摘要翻译： 一种用于为逐次逼近寄存器模拟到数字转换器和比较器共模电压来控制电源电压的方法和装置。 该方法包括：测量逐次逼近寄存器conversionTimestamp; 比较所述逐次逼近具有期望conversionTimestamp寄存器conversionTimestamp; 并且如果必要，执行所述供应和/或比较器共模电压的至少一个的闭环调整。 该装置中的共模电压调节器和校正模块的besteht。 共用模式电压调节器和校正模块包括相位 - 频率检测器，电荷泵，并且可以包括一个互导单元。
-
公开(公告)号：EP2228709A3
公开(公告)日：2014-05-07
申请号：EP10152718.2
申请日：2010-02-05
发明人： Kurokawa, Yoshiyuki
CPC分类号： G06F3/042 , G06F3/0412 , G06F3/0416 , H03M1/004 , H03M1/1215 , H03M1/46
摘要： An embodiment of the present invention provides a touch panel that enable data sensing with multi-gray scale and an electronic device. At least a first pixel including a first photosensor portion detecting light with a first color, a second pixel including a second photosensor portion detecting light with a second color, a first A/D converter performing A/D conversion on an output signal of the first photosensor portion, and a second A/D converter performing A/D conversion on an output signal of the second photosensor portion are included. The voltage resolution of the first A/D converter and the voltage resolution of the second A/D converter are different.
摘要翻译： 本发明的一个实施例提供了一种能够以多灰度级进行数据感测的触摸面板以及一种电子设备。 至少第一像素包括：第一光传感器部分，检测具有第一颜色的光;第二像素，包括检测具有第二颜色的光的第二光传感器部分;第一A / D转换器，对第一颜色的第一颜色的输出信号执行A / D转换 光传感器部分，以及对第二光传感器部分的输出信号执行A / D转换的第二A / D转换器。 第一个A / D转换器的电压分辨率和第二个A / D转换器的电压分辨率不同。
-
-
-
-
-
-
-
-
-
搜索结果
194 条记录 (耗时 0.023 秒)
