公开(公告)号：EP1837905A2

公开(公告)日：2007-09-26

申请号：EP07112163.6

申请日：2006-06-21

申请人： STMicroelectronics (Crolles 2) SAS ,  Koninklijke Philips Electronics N.V.

发明人： Torres, Joaquin ,  Gosset, Laurent-Georges

IPC分类号： H01L21/768

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an improved integrated circuit and integrated circuit fabrication method to introduce highly controlled air cavities within high-speed copper interconnects based on the introduction of a polymer material on the edges of the interconnect lines and vias within the interconnect stack, which incorporates and controls air cavities formation, thus enhancing the signal propagation performances of the semiconductor interconnects.

摘要翻译： 本发明提供了一种改进的集成电路和集成电路制造方法，其基于在互连线的壁上引入聚合物材料和互连叠层内的通孔，将高度控制的空气腔引入高速铜互连中， 控制空气腔形成，从而提高半导体互连的信号传播性能。

公开(公告)号：EP1724814A2

公开(公告)日：2006-11-22

申请号：EP06290775.3

申请日：2006-05-12

申请人： STMicroelectronics ( Crolles 2) SAS

发明人： Torres, Joaquin ,  Farcy, Alexis

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L27/0805 ,  H01L28/65

摘要： Un condensateur incorporé dans un circuit électronique intégré comprend deux armatures (1, 2) et une série de couches intermédiaires disposées entre les armatures. Les couches intermédiaires sont alternativement isolantes (10-13) et conductrices (21-23), et chaque couche conductrice (21-23) est isolée électriquement du reste du circuit. Un tel condensateur peut présenter une tension de claquage élevée.

摘要翻译： 该电路具有一个电容器，该电容器具有设置在下部和上部芯格栅（1,2）之间的一系列中间层，其中层包括导电层（21-23）和相同的绝缘层（10-13）。 下部核心网格的尺寸大于中间层和上部核心网格。 每个导电层设置在两个绝缘层之间。 每个导电层是电隔离的，使得导电层在电路的操作期间呈现浮动电位。 用于制造集成电子电路中存在的电容器的方法也包括独立权利要求。

公开(公告)号：EP1742260A3

公开(公告)日：2011-10-26

申请号：EP06291020.3

申请日：2006-06-21

申请人： STMicroelectronics (Crolles 2) SAS ,  NXP B.V.

发明人： Torres, Joaquin ,  Gosset, Laurent-Georges

IPC分类号： H01L21/768

CPC分类号： H01L21/7682

摘要： The invention relates to using properties of a hard mask liner (26) against the diffusion of a removal agent to prevent air cavities formation in specific areas of an interconnect stack. The inventive method includes defining a portion (14) on a surface of an IC interconnect stack as being specific to air cavity introduction where the defined portion is smaller than the surface of the substrate; producing at least one metal track within the interconnect stack and depositing at least one interconnect layer having a sacrificial material (18) and a permeable material (22) within the interconnect stack; defining at least one trench area (34) surrounding the defined portion and forming at least one trench; depositing a hard mask layer (26) to coat the trench; and forming at least one air cavity (32) below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant to.

公开(公告)号：EP1909319A1

公开(公告)日：2008-04-09

申请号：EP06301010.2

申请日：2006-10-03

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Torres, Joaquin ,  Farcy, Alexis

IPC分类号： H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76877 ,  H01L21/76889 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention concerns a method of forming an interconnect passing through an insulating layer in an integrated circuit, the method including the steps of forming a hole through the insulating layer; filling the hole with silicon; depositing a layer of metal covering one end of the hole; and performing heating such that the silicon in said hole reacts with the metal layer to form a metal compound throughout the depth of said hole.

摘要翻译： 本发明涉及一种在集成电路中形成穿过绝缘层的互连的方法，该方法包括以下步骤：通过绝缘层形成一个孔; 用硅填充孔; 沉积覆盖孔的一端的金属层; 并且进行加热，使得所述孔中的硅与所述金属层反应，以在所述孔的整个深度处形成金属化合物。

公开(公告)号：EP1837905A3

公开(公告)日：2008-12-31

申请号：EP07112163.6

申请日：2006-06-21

申请人： STMicroelectronics (Crolles 2) SAS ,  Koninklijke Philips Electronics N.V.

发明人： Torres, Joaquin ,  Gosset, Laurent-Georges

IPC分类号： H01L21/768

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an improved integrated circuit and integrated circuit fabrication method to introduce highly controlled air cavities within high-speed copper interconnects based on the introduction of a polymer material on the walls of the interconnect lines and vias within the interconnect stack, which incorporates and controls air cavities formation, thus enhancing the signal propagation performances of the semiconductor interconnects.

公开(公告)号：EP1742260A2

公开(公告)日：2007-01-10

申请号：EP06291020.3

申请日：2006-06-21

申请人： STMicroelectronics ( Crolles 2) SAS ,  Koninklijke Philips Electronics N.V.

发明人： Torres, Joaquin ,  Gosset, Laurent-Georges

IPC分类号： H01L21/768

CPC分类号： H01L21/7682

摘要： The invention relates to using properties of a hard mask liner against the diffusion of a removal agent to prevent air cavities formation in specific areas of an interconnect stack. The inventive method includes defining a portion on a surface of an IC interconnect stack as being specific to air cavity introduction where the defined portion is smaller than the surface of the substrate; producing at least one metal track within the interconnect stack and depositing at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack; defining at least one trench area surrounding the defined portion and forming at least one trench; depositing a hard mask layer to coat the trench; and forming at least one air cavity below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant to.

摘要翻译： 本发明涉及使用硬掩模衬垫（26）抵抗去除剂的扩散来防止在互连叠层的特定区域中形成空腔的性质。 本发明的方法包括在IC互连堆叠的表面上限定特定于空气引入的部分（14），其中限定部分小于衬底的表面; 在所述互连堆叠内产生至少一个金属轨道，并且在所述互连堆叠内沉积具有牺牲材料（18）和可渗透材料（22）的至少一个互连层; 限定围绕限定部分的至少一个沟槽区域（34）并形成至少一个沟槽; 沉积硬掩模层（26）以涂覆沟槽; 以及通过使用去除所述永久材料耐受的牺牲材料的去除剂，在所述表面的限定部分下方形成至少一个空气腔（32）。