公开(公告)号：EP3570167B1

公开(公告)日：2020-11-11

申请号：EP19172340.2

申请日：2019-05-02

申请人： STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

发明人： CRITELLI, Mr. Rosalino ,  GUARNACCIA, Mr. Giuseppe ,  LE-GOASCOZ, Ms. Delphine ,  ANQUET, Mr. Nicolas

IPC分类号： G06F11/10

公开(公告)号：EP3570167A1

公开(公告)日：2019-11-20

申请号：EP19172340.2

申请日：2019-05-02

申请人： STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

发明人： CRITELLI, Mr. Rosalino ,  GUARNACCIA, Mr. Giuseppe ,  LE-GOASCOZ, Ms. Delphine ,  ANQUET, Mr. Nicolas

IPC分类号： G06F11/10

摘要： A processing system (10) is described. The processing system comprises a bus system (120), a processing unit (102) and a non-volatile memory (104) configured to store at least one firmware (BL, FW) to be executed by the processing unit (102). A co-processor (108) is connected to the bus system (120), wherein the co-processor (108) comprises a register interface (110) comprising a plurality of registers (REG0..REGn) and a processing circuit (112) configured to perform at least one processing operation as a function of data stored in the registers (REG0..REGn). Specifically, the registers (REG0..REGn) comprise a first set of registers (SET1) configured to store a first set of configuration information and a second set of registers (SET2) configured to store a second set of configuration information.
Specifically, the register interface (110) comprises a bus interface (1102) configured to monitor write requests to the register interface (110), wherein the bus interface (1102) is configured to set for each register a respective register selection signal (WR_REG0..WR_REGn) when the target address of a write request corresponds to the address associated with a respective register. The register interface (110) comprises also a cyclic redundancy check calculation circuit (1118-1124) configured to compute a cyclic redundancy check value (CRC_INT) at least as a function of the data to be written (W_DATA) to the first set of registers (SET1) or a subset of registers thereof, and a masking circuit (1126). The masking circuit (1126) monitors the register selection signals (WR_REG0..WR_REGn) in order to determine the sequence of registers to which data has been stored and only when a comparison indicates that the sequence of registers corresponds to a reference sequence (REF_SEQ), the masking circuit (1126) provides the computed cyclic redundancy check value (CRC_INT) to the bus interface (1102).

公开(公告)号：EP3582134A1

公开(公告)日：2019-12-18

申请号：EP19177488.4

申请日：2019-05-30

申请人： STMicroelectronics S.r.l.

发明人： CRITELLI, Mr. Rosalino ,  GUARNACCIA, Mr. Giuseppe

IPC分类号： G06F21/71 ,  G06F21/74 ,  G06F21/85 ,  H04L9/06

摘要： A cryptographic method comprises providing memory locations (M) for storing encrypted data (RDATA_extmem), the memory locations (M) having respective addresses and being accessible via a communication bus (10, 20), receiving over the communication bus (10) access requests to the memory locations (M), wherein the access requests comprise burst requests for access to respective sets of the memory locations (M) starting from respective start addresses (ADDR), calculating as a function of the start addresses (ADDR) encryption/decryption cryptographic masks based on cryptographic keys, receiving (308) plain text data (plain_text) for encryption and applying (208) the cryptographic masks to the plain text data (plain_text) to obtain therefrom encrypted data, and including the encrypted data into output data (RDATA_otfdec) for transmission over the communication bus (20).

公开(公告)号：EP3537330A1

公开(公告)日：2019-09-11

申请号：EP19160360.4

申请日：2019-03-01

申请人： STMicroelectronics S.r.l.

发明人： GUARNACCIA, Mr. Giuseppe ,  CRITELLI, Mr. Rosalino

IPC分类号： G06F21/85 ,  G06F21/74 ,  H04L9/06

摘要： A method for data decryption comprises receiving (32), over an AXI bus (10) operating in burst mode, data access requests for data units stored in a memory (MC), subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory (MC), retrieving the respective sets of data units over the AXI bus (20), and applying Advanced Encryption Standard, AES, processing (60, 70, 80) to the requests for encrypted data units by calculating (72) decryption masks for the encrypted data units and applying (80) the decryption masks calculated to the encrypted data units retrieved.
Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.