公开(公告)号：EP4009174A3

公开(公告)日：2022-08-03

申请号：EP21209056.7

申请日：2021-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： BORGONOVO, Giampiero ,  RE FIORENTIN, Lorenzo

IPC: G06F11/16

Abstract: A hardware accelerator device comprises a set of processing circuits (160) arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network (162). The processing circuits (160) are configurable to read (200) first input data from said data memory banks via the interconnect network (162) and the memory controller, process (20) said first input data to produce output data, and write (204) said output data into said data memory banks via the interconnect network (162) and the memory controller. The hardware accelerator device comprises a set of configurable lockstep control units (169) which interface the processing circuits (160) to the interconnect network (162). Each configurable lockstep control unit (169) is coupled to a subset of processing circuits (160) and is selectively activatable to operate in a first operation mode, or in a second operation mode. In the first operation mode, the lockstep control unit (169) is configured to compare data read requests and/or data write requests issued towards said memory controller by a first (160 0 ) and a second (160 1 ) processing circuits in the subset of processing circuits to detect a fault. In the second operation mode, the lockstep control unit (169) is configured to propagate towards said memory controller said data read requests and/or data write requests issued by the first (160 0 ) and by the second (160 1 ) processing circuits in the subset of processing circuits (160).

公开(公告)号：EP4343563A1

公开(公告)日：2024-03-27

申请号：EP23194653.4

申请日：2023-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： BORGONOVO, Giampiero ,  RE FIORENTIN, Lorenzo

IPC: G06F13/38

Abstract: A system (1000), for use in providing MAC/router/switch/gateway features in an on-board communication network in a vehicle, for instance, comprises:
media access control, MAC controllers (1001) configured to provide a MAC port layer controlling exchange of information over a data link (Ethernet/CAN/LIN),
virtual machine, VM bridge blocks (1004) configured to provide a MAC frame layer interfacing with System-on-Chip, SoC virtual machines, VMs,
a software, SW Ethernet port (1005) configured to receive from a host programming/configuration information for the system (1000),
a local memory controller (1007) configured to facilitate the MAC controllers (1001), the VM bridge blocks and the SW Ethernet port (1005) in co-operating with a local memory (LMEM), and
queue handlers (1006A, 1006B and 1006C) configured to provide queue management for the MAC controllers (1001), the VM bridge blocks (1004) and the SW Ethernet port (1005), during co-operation with the local memory (LMEM) via the local memory controller (1007).

公开(公告)号：EP4009174A2

公开(公告)日：2022-06-08

申请号：EP21209056.7

申请日：2021-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： BORGONOVO, Giampiero ,  RE FIORENTIN, Lorenzo

IPC: G06F11/16

Abstract: A hardware accelerator device comprises a set of processing circuits (160) arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network (162). The processing circuits (160) are configurable to read (200) first input data from said data memory banks via the interconnect network (162) and the memory controller, process (20) said first input data to produce output data, and write (204) said output data into said data memory banks via the interconnect network (162) and the memory controller. The hardware accelerator device comprises a set of configurable lockstep control units (169) which interface the processing circuits (160) to the interconnect network (162). Each configurable lockstep control unit (169) is coupled to a subset of processing circuits (160) and is selectively activatable to operate in a first operation mode, or in a second operation mode. In the first operation mode, the lockstep control unit (169) is configured to compare data read requests and/or data write requests issued towards said memory controller by a first (160 0 ) and a second (160 1 ) processing circuits in the subset of processing circuits to detect a fault. In the second operation mode, the lockstep control unit (169) is configured to propagate towards said memory controller said data read requests and/or data write requests issued by the first (160 0 ) and by the second (160 1 ) processing circuits in the subset of processing circuits (160).

公开(公告)号：EP3093686A1

公开(公告)日：2016-11-16

申请号：EP15197855.8

申请日：2015-12-03

Applicant: STMicroelectronics S.r.l.

Inventor： BORGONOVO, Giampiero ,  MONTAGNANA, Marco

IPC: G01S7/292 ,  G01S13/524

CPC classification number: G01S13/931 ,  G01S7/2806 ,  G01S7/2922 ,  G01S7/2927 ,  G01S13/5246 ,  G01S2013/0245

Abstract: An accelerator device (10) for use in generating a list of potential targets (122) in a radar system such as an anti-collision radar for a motor vehicle such as e.g. a motorcar by processing radar data signals arranged in cells stored in a system memory. A cell under test (100) in the radar signals is identified as a potential target if the cell under test (100) is a local peak over boundary cells (BN) and is higher than a certain threshold (114) calculated (110, 112) by sorting (108) range and velocity radar data signals arranged in windows (WN), and the cells identified as a potential target are sorted (120) in a sorted list (122) of potential targets.
The accelerator device (10) includes:
- a double-buffering local memory (12) for storing cell under test and boundary cell data; and
- a first (14) and a second (16) sorting unit for performing concurrent sorting of the radar data signals arranged in windows (WN) and the cells identified as a potential target (122) in pipeline with accesses (20, 22) to the system memory.

Abstract translation: 加速器装置（10），用于在一个雷达系统中产生的潜在目标（122）的列表：如在防撞雷达用于机动车辆：如大肠杆菌G. 一个汽车通过处理雷达数据信号在存储在系统的存储器单元地布置。 下的雷达信号测试（100）的细胞被识别为潜在目标，如果受测试的单元（100）是在边界小区的局部峰值（BN）和比计算值（110，112一定的阈值（114）更高 ）通过在潜在目标排序列表（122）排序布置（108）的距离和速度雷达数据信号（在windows WN），和鉴定为潜在的目标细胞进行排序（120）。 加速器装置（10）包括： - 用于存储被测和边界单元数据单元的双缓冲本地存储器（12）; 以及 - 分类单元，用于执行在窗口（WN）布置在所述雷达数据信号的并行分选的第一（14）和第二（16）和在管道识别为潜在的目标（122）与访问单元（20，22） 到系统内存。

公开(公告)号：EP4067918A1

公开(公告)日：2022-10-05

申请号：EP22160090.1

申请日：2022-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： RE FIORENTIN, Lorenzo ,  BORGONOVO, Giampiero

IPC: G01R31/3187 ,  G01R31/3185

Abstract: Test stimulus signals (IN_TEST_DATA) applied to at least one circuit under test (200) are produced in a set of test stimulus generators (12) as a function of test stimulus information loaded in test stimulus registers (LFSR_1_1, LFSR_1_2, ..., LFSR_M_NM). Loading of test stimulus information in the test stimulus registers is controlled (16; LFSR_1_1_CTRL, LFSR_1_2_CTRL, ..., LFSR_M_NM_CTRL) as a function of test programming information (START, MULTI_CYCLE, TIMER MODE, N_CAPTURE_CYCLES, N_TSESSIONS_x_x, N_TCYCLES_x_x) loaded via a programming interface (APB) in a respective control register (LBIST_1_1_CTRL_REG, LBIST_1_2_CTRL_REG, ..., LBIST_M_NM_CTRL_REG) in a set of control registers (18). The test stimulus generators (12) are activated as a function of the test programming information loaded in said control registers (18). Test outcome signals (OUT_TEST_DATA_1, ..., OUT_TEST_DATA_X1+X2+...+XN-1+XN) received from the at least one circuit under test (200) in response to the stimulus signals (IN_TEST_DATA) being applied are used to produce (32) signature comparison signals (COMPRESSOR_1, COMPRESSOR_2, ... COMPRESSOR_N) which are compared with respective programmable (APB) signature reference signals stored in a set of input signature registers (SIGNATURE_1_G, SIGNATURE _2_G, ..., SIGNATURE_N_G). Error signals (ERR_1, ..., ERR_N) are produced in response to the signature comparison signals produced (32) from the test outcome signals received from the at least one circuit under test (200) failing to match with the respective reference signals.

公开(公告)号：EP3093686B1

公开(公告)日：2018-04-11

申请号：EP15197855.8

申请日：2015-12-03

Applicant: STMicroelectronics S.r.l.

Inventor： BORGONOVO, Giampiero ,  MONTAGNANA, Marco

IPC: G01S7/292 ,  G01S13/524

CPC classification number: G01S13/931 ,  G01S7/2806 ,  G01S7/2922 ,  G01S7/2927 ,  G01S7/354 ,  G01S13/003 ,  G01S13/42 ,  G01S13/5246 ,  G01S2013/0245

Abstract: An accelerator device (10) for use in generating a list of potential targets (122) in a radar system such as an anti-collision radar for a motor vehicle such as e.g. a motorcar by processing radar data signals arranged in cells stored in a system memory. A cell under test (100) in the radar signals is identified as a potential target if the cell under test (100) is a local peak over boundary cells (BN) and is higher than a certain threshold (114) calculated (110, 112) by sorting (108) range and velocity radar data signals arranged in windows (WN), and the cells identified as a potential target are sorted (120) in a sorted list (122) of potential targets. The accelerator device (10) includes: - a double-buffering local memory (12) for storing cell under test and boundary cell data; and - a first (14) and a second (16) sorting unit for performing concurrent sorting of the radar data signals arranged in windows (WN) and the cells identified as a potential target (122) in pipeline with accesses (20, 22) to the system memory.