公开(公告)号：EP4262091A1

公开(公告)日：2023-10-18

申请号：EP23161535.2

申请日：2023-03-13

Applicant: STMicroelectronics S.r.l.

Inventor： FORTUNATO, Davide Nicolo ,  CALCAGNO, Antonino ,  VINCIGUERRA, Marco ,  SCUDERI, Angelo ,  COSENTINO, Gaetano

IPC: H03L7/087 ,  H03L7/099 ,  H03L7/113

Abstract: A voltage-controlled oscillator, VCO in a PLL circuit is calibrated via a dichotomous search in a set of candidate frequency bands (0, 31) via a sequence of subsequent halving steps (that produce reduced subsets (0, 15; 7, 15; 11, 15; 13, 15; 12, 14; 12, 13) of the set of candidate frequency bands (0, 31). The reduced subsets (0, 15; 7, 15; 11, 15; 13, 15; 12, 14; 12, 13) have respective upper bound values (max; 15, 15, 15, 15, 14, 13), lower bound values (min; 0, 7, 11, 13, 12, 12) as well as central values (center; 7, 11, 13, 14, 13, 12). The central value of the subset resulting from the halving step of index i in the sequence is a function of the average ((max + min/2)) of the upper bound value (max) and the lower bound (min) value of the subset resulting from the halving step of index i-1 in the sequence.

公开(公告)号：EP3327930A1

公开(公告)日：2018-05-30

申请号：EP17177618.0

申请日：2017-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： SCUDERI, Angelo ,  ALESSI, Gesualdo ,  CALCAGNO, Antonino ,  MAIELLARO, Giorgio ,  SCACCIANOCE, Salvatore

IPC: H03F1/30 ,  H03F3/72 ,  H03F3/189 ,  H03F3/45 ,  H03G3/34 ,  H03G3/30

CPC classification number: H03G3/34 ,  H03F1/0216 ,  H03F1/305 ,  H03F3/189 ,  H03F3/19 ,  H03F3/21 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/451 ,  H03F2203/7221 ,  H03G1/0023 ,  H03G3/3005 ,  H03G3/3042 ,  H03G3/3047

Abstract: The present disclosure relates to solutions for switching on and off a power amplifier (20) comprising a signal input for receiving an input signal ( IN) and a signal output for providing an output signal ( OUT). The power amplifier (20) comprises also a control input for receiving a gain control signal (A INT ) being indicative of a requested gain and a control input for receiving a mute control signal (MUTE INT ) indicating whether the signal output should be switched on or switched off. A control unit (42) is associated with the power amplifier (20). The control unit (42) determines (420) whether the signal output of the power amplifier (20) should be switched on and/or off.

公开(公告)号：EP3528006A1

公开(公告)日：2019-08-21

申请号：EP19155320.5

申请日：2019-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： BELFIORE, Francesco ,  SCACCIANOCE, Salvatore ,  MICHELIN SALOMON, Amedeo ,  CALCAGNO, Antonino

IPC: G01S13/93 ,  G01S7/35 ,  G01S13/42 ,  G01S13/536 ,  G01S13/34

Abstract: A radar sensor circuit (10) for use, for example, in FMCW radar sensor systems installed on board of motorcars (V) comprises:
- an input node (18) receiving a received signal (RF_signal) chirp-modulated with a sequence of chirp ramps and down-converting the received signal to an intermediate frequency signal;
- a high-pass filter circuit (221, 222) which receives the intermediate frequency signal and produces therefrom a high-pass filtered signal (OS).
The high-pass filter circuit (221, 222) comprises first (221) and second (222) high-pass filtering arrangements with first (HPF1) and second (HPF2) corner frequencies, respectively, with the first corner frequency (HPF1) higher than the second corner frequency (HPF2). The high-pass filter circuit (221, 222) provides at each chirp in the chirp modulation high-pass filtering of the intermediate frequency signal starting with first high-pass filtering (221) subsequently replaced by second high-pass filtering (222) .