公开(公告)号：EP4262091A1

公开(公告)日：2023-10-18

申请号：EP23161535.2

申请日：2023-03-13

Applicant: STMicroelectronics S.r.l.

Inventor： FORTUNATO, Davide Nicolo ,  CALCAGNO, Antonino ,  VINCIGUERRA, Marco ,  SCUDERI, Angelo ,  COSENTINO, Gaetano

IPC: H03L7/087 ,  H03L7/099 ,  H03L7/113

Abstract: A voltage-controlled oscillator, VCO in a PLL circuit is calibrated via a dichotomous search in a set of candidate frequency bands (0, 31) via a sequence of subsequent halving steps (that produce reduced subsets (0, 15; 7, 15; 11, 15; 13, 15; 12, 14; 12, 13) of the set of candidate frequency bands (0, 31). The reduced subsets (0, 15; 7, 15; 11, 15; 13, 15; 12, 14; 12, 13) have respective upper bound values (max; 15, 15, 15, 15, 14, 13), lower bound values (min; 0, 7, 11, 13, 12, 12) as well as central values (center; 7, 11, 13, 14, 13, 12). The central value of the subset resulting from the halving step of index i in the sequence is a function of the average ((max + min/2)) of the upper bound value (max) and the lower bound (min) value of the subset resulting from the halving step of index i-1 in the sequence.

公开(公告)号：EP4274095A1

公开(公告)日：2023-11-08

申请号：EP23162910.6

申请日：2023-03-20

Applicant: STMicroelectronics S.r.l.

Inventor： COSENTINO, Gaetano

IPC: H03F1/30 ,  H03F3/45 ,  H03F3/30 ,  H03F3/195 ,  H03G3/30

Abstract: A circuit (10) for use in a variable-gain amplifier circuit comprises an amplifier stage (100) with complementary positive (Pamp) and negative (Namp) amplifier branches having current flow paths therethrough cascaded in at least one flow line for a core current for the amplifier stage (100) between a supply node (VSUPPLY) and ground (GND), wherein the complementary positive (Pamp) and negative (Namp) amplifier branches have respective input nodes configured (101; C11, C12) to receive an input signal applied therebetween.
The circuit further comprises one or both of:
a current mirror loop (200) coupled (201, 202) to the respective input nodes of the complementary positive (Pamp) and negative (Namp) amplifier branches, wherein the current mirror loop (200) provides an adjustable (Iref) high-impedance bias source for the core current for the amplifier stage (100),
at least one stability network (300) having a gain bandwidth range (206, 207) and configured (2076) to receive at least one output signal (A) from the amplifier stage (100) as well as an output voltage setting signal (DCS, VO) and based thereon, control (A, 208) the amplifier stage (100) to short-circuit the output signal (A) from the amplifier stage (100) within the gain bandwidth range (206, 207). The related solutions facilitate providing high-linearity, low-noise amplifiers exhibiting a high power supply rejection ratio, PSRR suitable to provide wide gain range variations without introducing a stability network function for a specific gain setting.

公开(公告)号：EP1598932A1

公开(公告)日：2005-11-23

申请号：EP04102176.7

申请日：2004-05-18

Applicant: STMicroelectronics S.r.l.

Inventor： COSENTINO, Gaetano ,  CALI', Giovanni ,  TORRISI, Felice ,  PELLERITI, Roberto

IPC: H03F1/22

CPC classification number: H03F1/223 ,  H03F1/14 ,  H03F2200/301 ,  H03F2200/492 ,  H03F2200/72

Abstract: The present invention refers to a cascode amplifier suitable for amplifying a voltage signal present on the input terminal (IN). The amplifier comprises at least one first transistor (M11) comprising a non-drivable input terminal that coincides with the input terminal (IN) of the amplifier, a non-drivable output terminal and a drivable terminal connected to a first polarisation voltage (V3). The amplifier comprises in addition at least one second transistor (M2) comprising a non-drivable input terminal in common with the output terminal of the first transistor (M11), an output terminal (OUT) non-drivable connected to a second polarisation voltage (V1) and a drivable terminal. The amplifier also comprises a feedback element (Rf, C2) placed between the output terminal (OUT) of the second transistor (M2) and the drivable terminal of the first transistor (M11) and circuit means (Cff, 100) coupled between the drivable terminals of the first (M11) and of the second (M2) transistor and suitable for making the values of voltage on the drivable terminal and on the output terminal of the first transistor (M11) substantially the same (Fig. 3).

Abstract translation: 本发明涉及一种适于放大输入端（IN）上存在的电压信号的共源共栅放大器。 放大器包括至少一个第一晶体管（M11），其包括与放大器的输入端（IN）重合的不可驱动的输入端子，不可驱动的输出端子和连接到第一极化电压（V3）的可驱动端子， 。 放大器还包括至少一个第二晶体管（M2），其包括与第一晶体管（M11）的输出端子共同的不可驱动的输入端子，不可驱动的输出端子（OUT）连接到第二极化电压（ V1）和可驱动的终端。 放大器还包括放置在第二晶体管（M2）的输出端（OUT）和第一晶体管（M11）的可驱动端子之间的反馈元件（Rf，C2）和耦合在可驱动的 （M11）和第二（M2）晶体管的端子，适于使第一晶体管（M11）的可驱动端子和输出端子上的电压值基本相同（图3）。

公开(公告)号：EP4274096A1

公开(公告)日：2023-11-08

申请号：EP23162897.5

申请日：2023-03-20

Applicant: STMicroelectronics S.r.l.

Inventor： COSENTINO, Gaetano

IPC: H03F3/45 ,  H03F3/195 ,  H03G3/30

Abstract: A variable-gain amplifier circuit comprises an amplifier (100) having at least one input node (101) configured to receive an input signal (IN) and at least one output node (102) configured to provide an output signal (RF Output). The output signal (RF Output) is a replica of the input signal (IN) having a variable gain applied thereto. At least one feedback network (Zpar; Zser) is provided comprising a variable-impedance feedback branch (Zpar) configured to couple the output node (102) and the input node (101) of the amplifier (100). The gain applied to the input signal (IN) is thus controllable by varying the impedance of the variable-impedance feedback branch (Zpar). The variable-impedance feedback branch (Zpar) comprises a plurality of sections (S1, S2, S3) having associated insertion switch circuitry (SW_low, SW_mid, SW_high) that can be controllably (CU) switched between a conductive state wherein a variable impedance feedback signal path from the output node 102) to the input node (101) of the amplifier (100) is provided through one or more selected sections (S1, S2 or S3) of the variable-impedance feedback branch (Zpar) having the respective insertion switch circuitry (SW_low, SW_mid, SW_high) in the conductive state while a feedback signal path from the output node (102) to the input node (101) of the amplifier (100) is interrupted in the other section(s) having the respective insertion switch circuitry (SW_low, SW_mid, SW_high) in a non-conductive state.