-
公开(公告)号：EP1014441B1
公开(公告)日：2009-08-05
申请号：EP98830771.6
申请日：1998-12-22
IPC分类号： H01L21/8239 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).
-
2.发明公开Floating gate non-volatile memory cell and process for manufacturing 审中-公开Schwebegate-Festwertspeicherzelle und Herstellungsverfahren
公开(公告)号：EP1786036A1
公开(公告)日：2007-05-16
申请号：EP05110648.2
申请日：2005-11-11
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for manufacturing a non-volatile memory cell including a floating gate MOS transistor, comprising the steps of: forming a gate dielectric ( 290 ) over a surface ( 210 ) of a semiconductor material layer ( 200 ); forming a conductive floating gate electrode ( 280 ) insulated from the semiconductor material layer by the gate dielectric; forming at least one isolation region ( 270 ) laterally to said floating gate electrode; excavating the at least one isolation region; filling the excavated isolation region with a conductive material; and forming a conductive control gate electrode ( 260 ) of the floating gate MOS transistor insulatively over the floating gate, wherein the step of forming the floating gate electrode includes: laterally aligning said floating gate electrode to the at least one isolation region; and the step of excavating includes: lowering an isolation region exposed surface below a floating gate electrode exposed surface, said lowering exposing walls of the floating gate electrode; forming a protective layer on exposed walls of the floating gate electrode; and etching the at least one isolation region essentially down to the gate dielectric, the protective layer protecting against etching a portion of the at least one isolation region near the gate dielectric.
摘要翻译： 一种用于制造包括浮置栅极MOS晶体管的非易失性存储单元的方法，包括以下步骤：在半导体材料层（200）的表面（210）上形成栅极电介质（290）; 形成通过栅极电介质与半导体材料层绝缘的导电浮栅电极（280）; 与所述浮栅电极横向形成至少一个隔离区域（270）; 挖掘所述至少一个隔离区域; 用导电材料填充挖掘的隔离区; 以及在所述浮置栅极上绝缘地形成所述浮置栅极MOS晶体管的导电控制栅极（260），其中形成所述浮置栅电极的步骤包括：将所述浮置栅电极横向对准所述至少一个隔离区域; 并且挖掘步骤包括：降低浮栅电极暴露表面下方的隔离区暴露表面，所述浮栅电极的所述降低暴露壁; 在浮栅电极的暴露壁上形成保护层; 并且将所述至少一个隔离区域基本上刻蚀到所述栅极电介质，所述保护层防止蚀刻栅极电介质附近的所述至少一个隔离区域的一部分。
-
3.发明公开
公开(公告)号：EP1014441A1
公开(公告)日：2000-06-28
申请号：EP98830771.6
申请日：1998-12-22
IPC分类号： H01L21/8239 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).
摘要翻译： 形成用于LV晶体管的源区和漏区（48'，55'）的步骤包括以下步骤：向LV栅区（43a）横向形成牺牲隔离物（101）; 以牺牲间隔物（101）自对准的方式形成LV源极和漏极区（55'）; 去除牺牲隔离物（101）; 形成HV晶体管的HV栅极区域（43d）; 形成选择晶体管的栅极区域（43c）; 形成存储晶体管的控制栅极区域（43b）; 同时形成与LV栅极区域（43a）自身对准的LDD区域（48'），与HV栅极区域（43d），源极和漏极区域（65a，65b）自身对准的HV源极和漏极区域（64） 与选择栅极区域（43c）和浮动栅极区域（27b）对准; 沉积介电层; 用保护硅化物掩模（72）覆盖HV和存储区域; 各向异性地蚀刻介电层，以在LV栅极区域（43a）的横向形成永久间隔物（52'）。 去除保护硅化物掩模（72）; 以及在LV源极和漏极区域（48'，55'）和LV栅极区域（43a）上形成硅化物区域（75a1,75a2）。
-
-
搜索结果
3 条记录 (耗时 0.009 秒)
