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    EEPROM with common control gate and common source for two cells
    3.
    发明公开
    EEPROM with common control gate and common source for two cells 审中-公开
    来自“简明英汉词典”

    公开(公告)号：EP0996161A1

    公开(公告)日：2000-04-26

    申请号：EP98830627.0

    申请日：1998-10-20

    申请人： STMicroelectronics S.r.l.

    发明人： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： The electronic device comprises pairs of memory cells (61a, 61b), formed in a same active area (9) of a substrate (2) of semiconductor material. Each cell is formed by a selection transistor (63a, 63b) and by a memory transistor (64a, 64b) of the floating gate and double polysilicon layer type. The memory transistors (64a, 64b) of the coupled cells have control gate regions formed by a single continuous gate region (43c) of semiconductor material extending over the respective floating gate regions (30a, 30b) and on the sides thereof which are reciprocally face-to-face, and on the zone of the substrate (2) accommodating a common source line (28).

    摘要翻译： 电子器件包括形成在半导体材料的衬底（2）的相同有源区域（9）中的成对存储单元（61a，61b）。 每个单元由选择晶体管（63a，63b）和浮置栅极和双多晶硅层类型的存储晶体管（64a，64b）形成。 耦合单元的存储晶体管（64a，64b）具有由半导体材料的单个连续栅极区域（43c）形成的控制栅极区域，该半导体材料在相应的浮动栅极区域（30a，30b）上延伸并且在其侧面上是相互面对的 并且在容纳公共源极线（28）的基板（2）的区域上。

    Method for realizing a multilevel ROM memory in a dual gate CMOS process and corresponding ROM memory cell
    4.
    发明公开
    Method for realizing a multilevel ROM memory in a dual gate CMOS process and corresponding ROM memory cell 有权
    一种用于在双栅极CMOS工艺制备多级ROM存储器和相应ROM存储器单元的过程

    公开(公告)号：EP0991118A1

    公开(公告)日：2000-04-05

    申请号：EP98830583.5

    申请日：1998-10-02

    申请人： STMicroelectronics S.r.l.

    发明人： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

    IPC分类号： H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/112 ,  H01L27/105 ,  H01L27/11253 ,  H01L27/11293

    摘要： The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type, which method comprises at least the following steps:

    on a semiconductor substrate, defining respective active areas for transistors of ROM cells (1), electrically erasable non-volatile memory cells, and low- and high-voltage transistors;
    depositing a layer of gate oxide over said active areas;
    depositing a polysilicon layer over the gate oxide layer;
    masking, and then etching, the polysilicon layer to define, by successive steps, respective gate regions of the ROM cells, non-volatile cells, and low- and high-voltage transistors;
    characterized in that it further comprises the following steps:
    masking the polysilicon layer (4) of some of the transistors of the ROM cells (1), and implanting a first dopant species (N) in the active areas (2) of the exposed transistors;
    removing the mask from the polysilicon layer (4), and implanting a second dopant species (P) in said previously covered layer;
    masking and subsequently etching the polysilicon layer to define the gate regions of the ROM cell transistors.

    摘要翻译： 本发明涉及生产在双栅型，该方法包括至少以下步骤中的一个CMOS工艺的ROM型的多级存储器的方法，包括：在半导体基片， - 定义respectivement有源区为ROM单元的晶体管 （1），电可擦除非易失性存储器单元，和低和高电压晶体管; 沉积在所述有源区的栅氧化层; 沉积在栅极氧化物层上的多晶硅层; 掩模，然后蚀刻，对多晶硅层进行定义，通过连续的步骤，所述ROM单元，非易失性单元，和低和高电压晶体管的栅极respectivement区; 其特征在于，这样做是还包括以下步骤：掩盖多晶硅层（4）的一些ROM单元的晶体管的（1），以及植入在有源区域的第一掺杂种类（N）（2）的暴露的晶体管 ; 从多晶硅层（4）除去掩模，并在注入。所述第二掺杂剂物种（P）之前覆盖层; 掩蔽并随后蚀刻所述多晶硅层，以限定所述ROM单元晶体管的栅极区域。

    Method for manufacturing EEPROM with periphery
    5.
    发明授权
    Method for manufacturing EEPROM with periphery 有权
    与外围EEPROM的制造方法

    公开(公告)号：EP1014441B1

    公开(公告)日：2009-08-05

    申请号：EP98830771.6

    申请日：1998-12-22

    申请人： STMicroelectronics S.r.l.

    发明人： Patelmo, Matteo ,  Vajana, Bruno ,  Dalla Libera, Giovanna ,  Cremonesi, Carlo ,  Galbiati, Nadia

    IPC分类号： H01L21/8239 ,  H01L27/105

    CPC分类号： H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

    摘要： The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).

    Non-volatile semiconductor memory
    8.
    发明公开
    Non-volatile semiconductor memory 审中-公开
    非易失性半导体存储器

    公开(公告)号：EP1033754A1

    公开(公告)日：2000-09-06

    申请号：EP99830111.3

    申请日：1999-03-03

    申请人： STMicroelectronics S.r.l.

    发明人： Dalla Libera, Giovanna ,  Patelmo, Matteo ,  Vajana, Bruno ,  Galbiati, Nadia

    IPC分类号： H01L27/115 ,  H01L29/423

    CPC分类号： H01L29/42324 ,  H01L27/115

    摘要： To increase the facing surface and thus the coupling between the floating gate (10a) and control gate (11a) regions of a memory cell (26a), the floating gate (10a) and control gate (11a) regions have a width which is not constant in different section planes parallel to a longitudinal section plane (50) extending through the source (5) and drain (6) regions of the cell. In particular, the width of the floating gate (10a) and control gate (11a) regions is smallest in the longitudinal section plane (50) and increases linearly in successive parallel section planes moving away from the longitudinal section plane.

    摘要翻译： 为了增加存储单元（26a）的浮置栅极（10a）和控制栅极（11a）区域之间的面对表面以及因此的耦合，浮置栅极（10a）和控制栅极（11a）区域的宽度不是 在平行于延伸通过电池的源极（5）和漏极（6）区域的纵向截面（50）的不同截面中恒定。 特别地，浮动栅极（10a）和控制栅极（11a）区域的宽度在纵向截面（50）中最小，并且在远离纵向截面的连续平行部分平面中线性增加。

    Simplified DPCC process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells
    9.
    发明公开
    Simplified DPCC process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells 有权
    FLFX-EEPROM-speicherzellen的Verfahren zum Herstellen von nicht selbstausgerichteten

    公开(公告)号：EP0994512A1

    公开(公告)日：2000-04-19

    申请号：EP98830612.2

    申请日：1998-10-15

    申请人： STMicroelectronics S.r.l.

    发明人： Dalla Libera, Giovanna ,  Vajana, Bruno

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： The invention relates to a simplified DPCC process for making non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith, the process comprising at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1. The process further comprises the following steps: poly1 masking to fully define the floating gate of the cell, the poly1 being removed from the area of the selection transistor during this step; depositing or growing the interpoly dielectric and forming tunnel oxide and interpoly dielectric; depositing or growing the interpoly dielectric and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the circuitry; depositing and doping a second polysilicon layer poly2; masking the second later of polysilicon to define the control and selection gate; poly etching in the matrix as far down as the intermediate dielectric layer; poly etching in the circuitry the whole short-circuited poly1/poly2 stack.

    摘要翻译： 本发明涉及一种用于制造FLOTOX EEPROM类型的非自对准浮栅半导体存储单元的简化DPCC工艺，该浮动栅极半导体存储单元被并入具有与其相关联的控制电路的单元阵列，其中每个单元具有与之相关联的选择晶体管，该工艺包括 至少以下步骤：生长或沉积选择晶体管和电池的栅介质层; 隧道掩蔽以通过用于清洁半导体表面的专用蚀刻步骤限定隧道区域; 生长隧道氧化物; 沉积和掺杂第一多晶硅层poly1。 该方法还包括以下步骤：poly1掩蔽以完全限定电池的浮置栅极，在该步骤期间，poly1从选择晶体管的区域中去除; 沉积或生长多层电介质并形成隧道氧化物和互聚电介质; 沉积或生长多晶硅电介质并形成选择晶体管的整个栅极电介质，因此其将由先前生长或沉积的层叠的多晶硅介电层和栅极电介质组成; 矩阵掩蔽仅从电路中去除多晶硅电介质; 沉积和掺杂第二多晶硅层poly2; 掩蔽第二个多晶硅以定义控制和选择门; 基体中的多晶刻蚀作为中间介电层的下方; 电路中的多层蚀刻全部短路的poly1 / poly2堆叠。