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    Improved built-in self-test method and system
    1.
    发明公开
    Improved built-in self-test method and system 审中-公开
    Verbesserte eingebaute Selbsttestmethode und System

    公开(公告)号：EP1724788A1

    公开(公告)日：2006-11-22

    申请号：EP05104183.8

    申请日：2005-05-18

    申请人： STMicroelectronics S.r.l.

    发明人： Griseta, Antonio ,  Mazzone, Angelo ,  Penza, Luigi

    IPC分类号： G11C29/00

    CPC分类号： G11C29/10 ,  G11C11/41

    摘要： A method for testing a memory device (100) comprising an arrangement of a plurality of memory elements (104) is proposed. The method comprises a step for defining a first and a second scanning sequences for scanning the memory elements and a step for defining at least one test datum ({XX}). The method further includes the performance of at least once a succession of operations including:
    a) writing the test datum into the plurality of memory elements, accessing thereto according to the first scanning sequence;
    b) accessing each memory element according to the first scanning sequence, reading a content thereof and comparing the read content to the test datum, and writing thereinto a complement of said test datum;
    c) accessing each memory element according to the second scanning sequence, reading a content thereof and comparing the read content to the complement of the test datum, and writing thereinto said test datum;
    d) accessing each memory element according to the second scanning sequence, reading a content thereof and comparing the read content to the test datum, writing thereinto said complement of the test datum, and reading again the content thereof and comparing the read content to the complement of the test datum.

    摘要翻译： 提出了一种用于测试包括多个存储元件（104）的布置的存储器件（100）的方法。 该方法包括用于定义用于扫描存储器元件的第一和第二扫描序列的步骤以及用于定义至少一个测试数据（{XX}）的步骤。 该方法还包括至少执行一次连续的操作，包括：a）将测试数据写入到多个存储器元件中，根据第一扫描顺序访问它; b）根据第一扫描顺序访问每个存储元件，读取其内容并将读取的内容与测试数据进行比较，并将其写入所述测试数据的补码; c）根据第二扫描顺序访问每个存储器元件，读取其内容并将读取的内容与测试数据的补码进行比较，并将其写入所述测试数据; d）根据第二扫描顺序访问每个存储器元件，读取其内容并将读取的内容与测试数据进行比较，在其中写入测试数据的所述补码，并再次读取其内容，并将读取的内容与补码进行比较 的测试基准。

    Built-in self test circuit for integrated circuits
    2.
    发明公开
    Built-in self test circuit for integrated circuits 有权
    Eingebaute Selbsttestschaltungfürintegrierte Schaltungen

    公开(公告)号：EP1388788A1

    公开(公告)日：2004-02-11

    申请号：EP02425519.2

    申请日：2002-08-08

    申请人： STMicroelectronics S.r.l.

    发明人： Barone, Massimiliano ,  Griseta, Antonio

    IPC分类号： G06F11/267 ,  G01R31/3187

    CPC分类号： G06F11/27 ,  G01R31/3187

    摘要： A built-in self-test (BIST) circuit adapted to be embedded in an integrated circuit ( 101 ) for testing the integrated circuit, including in particular a collection of addressable elements, for example a semiconductor memory. The BIST circuit comprises a general-purpose data processor ( 105 ) programmable for executing a test program for testing the integrated circuit. The BIST circuit comprises an accelerator circuit ( 113 ) cooperating with the general-purpose data processor for autonomously conducting operations on the integrated circuit according to the test program. The accelerator circuit comprises configuration means ( 201,203,233,301,303,501 ) adapted to be loaded with configuration parameters for adapting the accelerator circuit to the specific type of integrated circuit and the specific type of test program. ( FIG. 1 )

    摘要翻译： 内置的自检（BIST）电路，适于嵌入集成电路（101）中，用于测试集成电路，特别包括可寻址元件的集合，例如半导体存储器。 BIST电路包括可编程用于执行用于测试集成电路的测试程序的通用数据处理器（105）。 BIST电路包括与通用数据处理器协作的加速器电路（113），用于根据测试程序自动地对集成电路进行操作。 加速器电路包括适于加载用于使加速器电路适应特定类型的集成电路的配置参数和特定类型的测试程序的配置装置（201,203,233,301,303,501）。 （图1）

    ECC for single 4-bits symbol correction of 32 symbols words based on a matrix having a maximum row weight matrix of 22
    4.
    发明公开
    ECC for single 4-bits symbol correction of 32 symbols words based on a matrix having a maximum row weight matrix of 22 有权
    用于基于矩阵具有22行的最大的最大重量的具有32个码元字的各自的4位符号校正的纠错码（ECC）

    公开(公告)号：EP1724686A1

    公开(公告)日：2006-11-22

    申请号：EP05104238.0

    申请日：2005-05-19

    申请人： STMicroelectronics S.r.l.

    发明人： Griseta, Antonio ,  Mazzone, Angelo

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1072

    摘要： An error correction device is provided. Such error correction device makes use of an error correction code defined by a parity matrix specialized for the application to multilevel memories. Particularly, the parity matrix is characterized by having a Maximum Row Weight equal to 22.

    摘要翻译： 一种纠错装置。 搜索纠错装置利用了由奇偶矩阵用于专门的应用到多级存储器定义的纠错码。 特别地，奇偶校验矩阵是由具有最大权重的行等于第22特征的