公开(公告)号：EP3872988A1

公开(公告)日：2021-09-01

申请号：EP21159784.4

申请日：2021-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： PASSI, Stefano ,  BARDELLI, Roberto Giorgio ,  MORONI, Anna

IPC: H03K4/02

Abstract: A waveform generator includes: a system control unit (2) and a plurality of channels, (3.1, ..., 3.N) controlled by the system control unit (2) and configured to supply driving signals (V1, ..., VM) for driving a respective one of an array of transducers (5.1, ..., 5.N). Each channel includes: a sequential access memory (10) having a plurality of rows, each containing instruction words (W) configured to generate a respective step of a waveform, and a memory output (10a) defined by an output row at a fixed location, the waveform being defined by a block of instruction words (W). Each channel also includes an internal control unit (12), configured to sequentially move the content of the sequential access memory (10), based on the instruction word (W) currently at the memory output (10a), so that sequences of instruction words (W) are provided at the output row (10a).

公开(公告)号：EP4328623A1

公开(公告)日：2024-02-28

申请号：EP23191619.8

申请日：2023-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： PASSI, Stefano ,  BARDELLI, Roberto Giorgio

IPC: G01S7/52 ,  G01S15/89

Abstract: A memory includes a sequence of memory locations storing a corresponding sequence of state codes that specifying the shape of a waveform. The sequence of state codes is read from the memory and decoded by a long and toggle decoder circuit. The decoding operation generates a sequence of signal codes. When the state code is a long code, the sequence of signal codes includes same signal codes corresponding to a signal level of the waveform. When the state code is a toggle code, the sequence of signal codes includes a first signal code corresponding to one signal level of the waveform and a second signal code corresponding to another signal level of the waveform. A signal decode circuit then decodes the signal codes in the sequence of signal codes to generate the waveform for output which includes the signal levels corresponding to the decoded signal codes.

公开(公告)号：EP4339641A1

公开(公告)日：2024-03-20

申请号：EP23192877.1

申请日：2023-08-23

Applicant: STMicroelectronics S.r.l.

Inventor： PASSI, Stefano ,  VITI, Marco

IPC: G01S7/52 ,  B06B1/02 ,  G10K11/34

Abstract: A signal decode circuit is coupled to a buffer for each signal channel. A memory includes a shared area configured to store waveform data sets, each waveform data set including a sequence of coded waveform values specifying waveform step states. The shared area further stores delay data sets, each delay data set including a digital delay value for each signal channel defining a delay profile. A signal pointer addresses the shared area to read one waveform data set from the memory with the sequence of coded waveform values being selectively loaded into one or more of the buffers. A delay pointer addresses the shared area to read one delay data set from the memory with the digital delay values used to control delayed actuation of the signal decode circuits to decode the sequence of coded waveform values from the buffers and generate waveform signals in accordance with the delay profile.