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公开(公告)号：EP4339641A1
公开(公告)日：2024-03-20
申请号：EP23192877.1
申请日：2023-08-23
发明人： PASSI, Stefano , VITI, Marco
摘要： A signal decode circuit is coupled to a buffer for each signal channel. A memory includes a shared area configured to store waveform data sets, each waveform data set including a sequence of coded waveform values specifying waveform step states. The shared area further stores delay data sets, each delay data set including a digital delay value for each signal channel defining a delay profile. A signal pointer addresses the shared area to read one waveform data set from the memory with the sequence of coded waveform values being selectively loaded into one or more of the buffers. A delay pointer addresses the shared area to read one delay data set from the memory with the digital delay values used to control delayed actuation of the signal decode circuits to decode the sequence of coded waveform values from the buffers and generate waveform signals in accordance with the delay profile.
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公开(公告)号：EP4050798A1
公开(公告)日：2022-08-31
申请号：EP22155544.4
申请日：2022-02-08
发明人： VITI, Marco
摘要： A multi-level pulser circuit (8) comprises a set of first input pins (HVPO, HVP1) for receiving respective positive voltage signals ( HV P0 , HV P1 ) at different voltage levels, a set of second input pins (HVNO, HVN1) for receiving respective negative voltage signals ( HV N0 , HV N1 ) at different voltage levels, and a reference input pin (GND) configured to receive a reference voltage signal ( GND ) intermediate said positive voltage signals ( HV P0 , HV P1 ) and said negative voltage signals ( HV N0 , HV N1 ). The circuit comprises an output pin (OUT) configured to supply a pulsed output signal ( OUT ) . The circuit further comprises control circuitry configured to selectively ( P0, P1, N0, N1, CL ) couple said output pin (OUT) to one of said first input pins (HVPO, HVP1), said second input pins (HVNO, HVN1) and said reference input pin (GND) to generate said pulsed output signal (OUT) at said output pin (OUT). The control circuitry is further configured to couple said output pin (OUT) to at least one pin selected in the group comprising said second input pins (HVNO, HVN1) and said reference input pin (GND) during falling transitions of said pulsed output signal (OUT) between two positive voltage levels, and couple said output pin (OUT) to at least one pin selected in the group comprising said first input pins (HVPO, HVP1) and said reference input pin (GND) during rising transitions of said pulsed output signal (OUT) between two negative voltage levels.
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