CAPACITOR CHARGING METHOD, CORRESPONDING CIRCUIT AND DEVICE

    公开(公告)号:EP4293864A1

    公开(公告)日:2023-12-20

    申请号:EP23175108.2

    申请日:2023-05-24

    Abstract: A capacitance (Cload) coupled to a source of electrical charge (S) via a drain-source current flow path through a field-effect transistor (M1), is precharged by making the field-effect transistor (M1) selectively conductive in response to the gate-source voltage (Vgs) of the field-effect transistor (M1) exceeding an (e.g., temperature-dependent) threshold (Vth). The difference between the gate-source voltage (Vgs) of the field-effect transistor (M1) and the threshold (Vth) provides an overdrive value of the field-effect transistor (M1). The gate of the field-effect transistor (M1) is driven with a variable gate-source voltage (Vgs) having as a target maintaining a constant overdrive value. Electrical charge is thus controllably transferred from the source (S) to the capacitance (Cload) via the drain-source current flow path through the field-effect transistor (M1) avoiding undesirably high inrush currents and hot spotting.

    REVERSE BATTERY PROTECTION CIRCUIT
    2.
    发明公开

    公开(公告)号:EP4297213A1

    公开(公告)日:2023-12-27

    申请号:EP23176695.7

    申请日:2023-06-01

    Abstract: A circuit for reverse battery protection (216) includes an isolation circuit (218) and a control circuit (220). The isolation circuit (218) is coupled between a gate output of an electronic fuse, E-fuse (202) and at least one external metal-oxide-semiconductor field-effect transistor,MOSFET (210). The E-fuse (202) is coupled between a battery voltage pin and an external ground pin and further coupled to a microcontroller (206). The isolation circuit (218) is configured to disconnect the gate output from the at least one external MOSFET (210) when the battery is installed with reverse polarity. The control circuit (220) is coupled between the external ground pin and the at least one external MOSFET (210). The control circuit (220) is configured to turn on the at least one external MOSFET (210) when the battery is installed with the reverse polarity.

    CURRENT ABSORPTION MANAGEMENT CIRCUIT, CORRESPONDING SYSTEM AND METHOD

    公开(公告)号:EP4012866A1

    公开(公告)日:2022-06-15

    申请号:EP21210682.7

    申请日:2021-11-26

    Abstract: A current absorption management circuit (10) for use in an electronic fuse, for instance, comprises a first node (VBAT+) and a second node (OUT) coupled to an electrical supply source (for instance a battery SS in a motor vehicle V) and an electrical load (L) supplied by the electrical supply source (SS) via an electronic switch (such as a power MOSFET transistor 12) having a control node). A third node (GD) of the circuit is coupled to the electronic switch (12) to switch the electronic switch (12) between a conductive state (1000), wherein the electrical load (L) is coupled to the supply source (SS) via the electronic switch (12), and a non-conductive state (1000A).
    A secondary electronic switch (12A) is arranged intermediate the first node (VBAT+) and the second node (OFF) and control logic circuitry (20) is provided configured to operate alternately:
    in a first (full ON) mode of operation (1000), wherein the electronic switch (12) is in a conductive state and the electrical load (L) is coupled to the supply source (SS) via the electronic switch (12), and the secondary electronic switch (12A) is in a non-conductive state, and
    in a second (ON active-standby) mode of operation (1002), wherein the electronic switch (12) is in a non-conductive state and the secondary electronic switch (12A) is in a conductive state and the electrical load (L) is coupled to the supply source (SS) via the secondary electronic switch (12A).

    ELECTRONIC DEVICE AND CORRESPONDING SELF-TEST METHOD

    公开(公告)号:EP3961229A1

    公开(公告)日:2022-03-02

    申请号:EP21190380.2

    申请日:2021-08-09

    Abstract: An electronic device (10) such as an e-fuse comprises analog circuitry configured to be set to one or more self-test configurations. To that effect the device comprises self-test controller circuitry (12) in turn comprising:
    an analog configuration and sensing circuit (16, 162) configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations,
    a data acquisition circuit (18, 182) configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and
    a fault event detection circuit (22, 222) configured to check the test signals converted to digital against reference parameters.
    The device (10) comprises integrated therein a self-test controller (12) configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer (120).

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