公开(公告)号：EP4224321A1

公开(公告)日：2023-08-09

申请号：EP23151393.8

申请日：2023-01-12

Applicant: STMicroelectronics S.r.l.

Inventor： TORTORA, Gianluca ,  BARONE, Mario

IPC: G06F11/10

Abstract: A processing system (10a) is described. The processing system (10a) comprises configuration registers (112) and a serial non-volatile memory (12a), wherein each memory slot stores configuration data (CD) and error detection bits (PD). A hardware configuration circuit (108a) sequentially reads the data from the non-volatile memory (12a) and store the data read to respective configuration registers (112) For this purpose, the hardware configuration circuit (108a) receives the bits (DATA) of a current memory slot. Next, the hardware configuration circuit (108a) selectively asserts an error signal (PD_ERR) by comparing the received error detection bits (PD) with calculated error detection bits. When the error signal (PD_ERR) is asserted, the hardware configuration circuit (108a) asserts a further error signal (PD _ERR') indicating whether the data of any of the already read memory slots comprise an error. When the further error signal (PD _ERR') is de-asserted, the hardware configuration circuit (108a) stores the received bits to temporary registers (1098). Otherwise, the hardware configuration circuit (108a) stores predetermined configuration data (DATA') to the temporary registers (1098). Next, the hardware configuration circuit (108a) sequentially stores (1096, 1100) the content of the temporary registers (1098) to respective configuration registers (112). Finally, once having received the data of all memory slots, the hardware configuration circuit (108a) generates a further reset signal (RST2) for resetting at least in part the content of the configuration registers (112) when the further error signal (PD _ERR') is asserted.