公开(公告)号：EP0080876A3

公开(公告)日：1985-07-10

申请号：EP82306313

申请日：1982-11-26

申请人： STORAGE TECHNOLOGY CORPORATION

发明人： Dodd, David P. ,  Blickenstaff, Ronald L. ,  Coulson, Richard L. ,  Moreno, Robert J. ,  Trede, Brian E.

IPC分类号： G11C09/06

CPC分类号： G06F12/0866 ,  G06F12/0862 ,  G06F2212/6026 ,  G06F2212/6028

摘要： A host computer (10) is backed up by long term secondary magnetic disk storage means (14) coupled to the computer by channels (12), a storage director (16) and a control module (18). A cache memory (22) with an associated cache manager (24) are also connected to the storage director (16) for storing data which the host computer (10) is likely to require. In order to allow automatic transfer to the cache memory (22) of only that data which is likely to be required, the storage director (16) and cache manager (24) determine when accessed data from the disk storage means (14) appears to be part of sequential data because it lacks indications to the contrary, such as embedded SEEK instructions. When data lacks such counter indications, automatic transfers to the cache memory (22) occur a track at a time.

公开(公告)号：EP0080875A2

公开(公告)日：1983-06-08

申请号：EP82306312.8

申请日：1982-11-26

申请人： STORAGE TECHNOLOGY CORPORATION

发明人： Dodd, David P.

IPC分类号： G06F13/12

CPC分类号： G06F12/0888 ,  G06F12/0866 ,  G06F2212/312

摘要： A host computer (10) has a plurality of channels (16,18) for writing data to and reading data from secondary memory means (26) such as disk memories, via directors (12,14) and control modules (24) for the secondary memories. In order to speed up memory accesses, a cache memory (30) is provided to receive data expected to be required by the host computer (10). A single cache memory (30) serves all directors (12,14). Data entered into the cache memory flows from a disk memory (26), a control module (24) therefor and a director (12 or 14) to the cache memory (30). Data flows to the host computer from the cache memory (30) through a director (12 or 14) and the corresponding channel (16 or 18). A microprocessor control unit (32) determines what data should be cached and memory allocation within the cache memory (30).

摘要翻译： 主计算机（10）具有多个通道（16,18），用于通过控制器（12,14）和控制模块（24）将数据写入数据并从二级存储器装置（26）读取数据，例如盘存储器 二级记忆 为了加速存储器访问，提供高速缓冲存储器（30）以接收预期由主计算机（10）需要的数据。 单个高速缓存存储器（30）用于所有控制器（12,14）。 输入高速缓冲存储器的数据从磁盘存储器（26），控制模块（24）和导向器（12或14）流向高速缓冲存储器（30）。 数据通过导向器（12或14）和对应的通道（16或18）从高速缓冲存储器（30）流向主计算机。 微处理器控制单元（32）确定高速缓冲存储器（30）中应该缓存什么数据和存储器分配。

公开(公告)号：EP0080875A3

公开(公告)日：1985-07-03

申请号：EP82306312

申请日：1982-11-26

申请人： STORAGE TECHNOLOGY CORPORATION

发明人： Dodd, David P.

IPC分类号： G11C09/06

CPC分类号： G06F12/0888 ,  G06F12/0866 ,  G06F2212/312

摘要： A host computer (10) has a plurality of channels (16,18) for writing data to and reading data from secondary memory means (26) such as disk memories, via directors (12,14) and control modules (24) for the secondary memories. In order to speed up memory accesses, a cache memory (30) is provided to receive data expected to be required by the host computer (10). A single cache memory (30) serves all directors (12,14). Data entered into the cache memory flows from a disk memory (26), a control module (24) therefor and a director (12 or 14) to the cache memory (30). Data flows to the host computer from the cache memory (30) through a director (12 or 14) and the corresponding channel (16 or 18). A microprocessor control unit (32) determines what data should be cached and memory allocation within the cache memory (30).

公开(公告)号：EP0080877A3

公开(公告)日：1985-06-26

申请号：EP82306314

申请日：1982-11-26

申请人： STORAGE TECHNOLOGY CORPORATION

发明人： Coulson, Richard L. ,  Blickenstaff, Ronald L. ,  Dodd, David P. ,  Moreno, Robert J. ,  Kinard, Dean P.

IPC分类号： G11C09/06

CPC分类号： G06F12/0866 ,  G06F2212/312 ,  G06F2212/601 ,  Y10S707/99956

摘要： A host computer (10) is backed up by magnetic disk stores (14) which may be of different types having different track lengths. The host computer is conventionally coupled tothe disk stores by channels (12), a storage director (16) and disk control modules (18). A solid-state cache memory array (22) with an associated cache manager (22) are connected to the storage director for storing tracks of data likely to be required by the host computer. In order to provide efficient utilisation of the cache memory array (22) it is arranged in domains having a length which is substantially an integral multiple of all the different track lengths. The domains are assigned to the different classes of disk storage devices (14) and reallocation is effected from time to time on the basis of actual usage.

摘要翻译： 主计算机（10）由可能具有不同类型的磁盘存储（14）备份，具有不同的磁道长度。 通常，主计算机通过通道（12），存储引导器（16）和盘控制模块（18）耦合到磁盘存储器。 具有相关联的高速缓存管理器（22）的固态高速缓冲存储器阵列（22）连接到存储引导器，用于存储主计算机可能需要的数据的轨道。 为了提供对高速缓冲存储器阵列（22）的有效利用，它被布置在具有基本上是所有不同轨道长度的整数倍的长度的域中。将域分配给不同类别的盘存储设备（14） 并根据实际使用情况不时进行重新分配。

公开(公告)号：EP0080875B1

公开(公告)日：1993-01-27

申请号：EP82306312.8

申请日：1982-11-26

申请人： STORAGE TECHNOLOGY CORPORATION

发明人： Dodd, David P.

IPC分类号： G06F13/12

CPC分类号： G06F12/0888 ,  G06F12/0866 ,  G06F2212/312

公开(公告)号：EP0080876B1

公开(公告)日：1989-02-01

申请号：EP82306313.6

申请日：1982-11-26

申请人： STORAGE TECHNOLOGY CORPORATION

发明人： Dodd, David P. ,  Blickenstaff, Ronald L. ,  Coulson, Richard L. ,  Moreno, Robert J. ,  Trede, Brian E.

IPC分类号： G06F12/12

CPC分类号： G06F12/0866 ,  G06F12/0862 ,  G06F2212/6026 ,  G06F2212/6028

公开(公告)号：EP0080877A2

公开(公告)日：1983-06-08

申请号：EP82306314.4

申请日：1982-11-26

申请人： STORAGE TECHNOLOGY CORPORATION

发明人： Coulson, Richard L. ,  Blickenstaff, Ronald L. ,  Dodd, David P. ,  Moreno, Robert J. ,  Kinard, Dean P.

IPC分类号： G11C9/06

CPC分类号： G06F12/0866 ,  G06F2212/312 ,  G06F2212/601 ,  Y10S707/99956

摘要： A host computer (10) is backed up by magnetic disk stores (14) which may be of different types having different track lengths. The host computer is conventionally coupled tothe disk stores by channels (12), a storage director (16) and disk control modules (18). A solid-state cache memory array (22) with an associated cache manager (22) are connected to the storage director for storing tracks of data likely to be required by the host computer. In order to provide efficient utilisation of the cache memory array (22) it is arranged in domains having a length which is substantially an integral multiple of all the different track lengths. The domains are assigned to the different classes of disk storage devices (14) and reallocation is effected from time to time on the basis of actual usage.

摘要翻译： 主计算机（10）由可能具有不同类型的磁盘存储（14）备份，具有不同的磁道长度。 通常，主计算机通过通道（12），存储引导器（16）和盘控制模块（18）耦合到磁盘存储器。 具有相关联的高速缓存管理器（22）的固态高速缓冲存储器阵列（22）连接到存储引导器，用于存储主计算机可能需要的数据的轨道。 为了提供对高速缓冲存储器阵列（22）的有效利用，它被布置在具有基本上是所有不同轨道长度的整数倍的长度的域中。将域分配给不同类别的盘存储设备（14） 并根据实际使用情况不时进行重新分配。

公开(公告)号：EP0080876A2

公开(公告)日：1983-06-08

申请号：EP82306313.6

申请日：1982-11-26

申请人： STORAGE TECHNOLOGY CORPORATION

发明人： Dodd, David P. ,  Blickenstaff, Ronald L. ,  Coulson, Richard L. ,  Moreno, Robert J. ,  Trede, Brian E.

IPC分类号： G06F12/12

CPC分类号： G06F12/0866 ,  G06F12/0862 ,  G06F2212/6026 ,  G06F2212/6028

摘要： A host computer (10) is backed up by long term secondary magnetic disk storage means (14) coupled to the computer by channels (12), a storage director (16) and a control module (18). A cache memory (22) with an associated cache manager (24) are also connected to the storage director (16) for storing data which the host computer (10) is likely to require. In order to allow automatic transfer to the cache memory (22) of only that data which is likely to be required, the storage director (16) and cache manager (24) determine when accessed data from the disk storage means (14) appears to be part of sequential data because it lacks indications to the contrary, such as embedded SEEK instructions. When data lacks such counter indications, automatic transfers to the cache memory (22) occur a track at a time.

摘要翻译： 主计算机（10）由通过通道（12），存储引导器（16）和控制模块（18）耦合到计算机的长期次级磁盘存储装置（14）支持。 具有相关联的高速缓存管理器（24）的高速缓冲存储器（22）也连接到存储引导器（16），用于存储主计算机（10）可能需要的数据。 为了允许只有那些可能需要的数据自动传送到高速缓冲存储器（22），存储控制器（16）和高速缓存管理器（24）确定来自盘存储装置（14）的访问数据何时显示为 作为顺序数据的一部分，因为它缺少相反的指示，如嵌入式SEEK指令。 当数据缺少这种计数器指示时，自动转移到高速缓冲存储器（22）一次发生轨道。