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    Block replacement in a high speed cache memory system
    3.
    发明公开
    Block replacement in a high speed cache memory system 失效
    在einem Schnellzugriffspeicher系统中的Blockaustausch。

    公开(公告)号：EP0009412A2

    公开(公告)日：1980-04-02

    申请号：EP79301974.6

    申请日：1979-09-24

    申请人： SPERRY CORPORATION

    发明人： De Karske, Clarence William

    IPC分类号： G11C9/06 ,  G06F13/00

    CPC分类号： G06F11/1666 ,  G06F11/20 ,  G06F12/126 ,  G06F2201/85 ,  G06F2212/1032 ,  G11C29/88

    摘要： The invention relates to computer memory,systems in which the main memory is divided into sets, and a high speed cache or buffer memory is provided which holds four blocks of words from each set of the main memory. When a new block is to be written into the cache memory one of the old blocks must be displaced to make way for it, and this is done in accordance with an algorithm determining which of the blocks was least recently used. In the prior art this algorithm has required the storage in the high speed cache memory of four digits per block, that is to say, eight digits for the four blocks of each set, and this takes up a substantial part of the expensive high speed storage. The present invention reduces this requirement to only three digits for each set of four blocks.
    The up-date algorithm is shown in Figure 2. The blocks are regarded as being in two pairs, AB and CD; a first digit, digit 2 is set to 0 or 1 according to the pair in which the accessed block lies; the second digit is set to 0 or 1 if the block lies in one pair, CD, to indicate which block of that pair was accessed, and similarly the third digit, digit 0, is set to 0 or 1 when a block of the other pair AB is accessed.
    A degrade memory can be provided in which a digit is set to indicate a faulty block in the buffer. This digit is supplied to the comparator and to the age algorithm circuits of the buffer memory to prevent the faulty block being accessed and to force the age digits to a value such that the block will never be displaced into, or re-written from, main memory.

    摘要翻译： 本发明涉及其中主存储器被划分成组的计算机存储系统，并且提供了一个高速缓存或缓冲存储器，其保存来自主存储器的每一组的四个字。 当一个新的块要被写入高速缓冲存储器时，其中一个旧的块必须被移位以使其变为可能，并且这是根据确定哪个块最近被使用的算法来完成的。 在现有技术中，该算法需要在每个块中存储四位数的高速高速缓冲存储器，也就是说，每组四个块的数字为8位，这占据了昂贵的高速存储器的大部分 。 本发明将这一要求仅将每一组四个块减少到三位数。 ... 最新算法如图2所示。块被认为是两对，AB和CD; 第一位，数字2根据访问块所在的对设置为0或1; 如果块位于一对CD中，则第二个数字被设置为0或1，以指示该对的哪个块被访问，并且类似地，当另一个的块的第二个数字0被设置为0或1时 对AB被访问。 ...可以提供降级存储器，其中设置数字以指示缓冲器中的故障块。 该数字提供给比较器和缓冲存储器的年龄算法电路，以防止访问故障块，并将年龄数字强制为使得该块永远不会被移位到主存储器中或从主存储器重写。

    Virtual memory address translation mechanism with combined hash address table and inverted page table
    4.
    发明公开
    Virtual memory address translation mechanism with combined hash address table and inverted page table 失效
    装置用于转换具有组合的混合寻址表和倒页表的虚拟存储器地址。

    公开(公告)号：EP0115179A2

    公开(公告)日：1984-08-08

    申请号：EP83307845.4

    申请日：1983-12-22

    申请人： International Business Machines Corporation

    发明人： Hester, Phillip Doyce ,  Simpson, Richard Ormond

    IPC分类号： G11C9/06 ,  G06F13/00

    CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0781 ,  G06F12/1036 ,  G06F12/1475 ,  G06F2212/683

    摘要： A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memories wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT).
    The system also has means for hashing a selected virtual address to produce a hashed address. Also included in apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.

    摘要翻译： 提供了一种用于转换页面帧中由CPU提供到实际存储器地址的虚拟存储器地址在一个大hierachial记忆worin实存储器空间中的虚拟存储器地址转换机制基本上大于虚拟存储器的范围小。 转换或平移机构包括其中包括覆盖每个存储器地址的respectivement虚拟地址（倒立页或IPT）和连接每个散列地址的多个以预定的初始虚拟地址的第二列表中的第一列表中的存储器的组合表 虚拟地址的链接组，其中每一个的当散列可生产所连接的散列地址（哈希表寻址，HAS）。 因此，该系统具有用于散列一个选择的虚拟地址以产生一个散列地址。 所以包括在装置，用于顺序地通过在组合的表的虚拟地址的链接的群搜索，直到所选择的虚拟地址位于以及响应于特定的位置装置选择的虚拟地址，用于从第一列表中访问，真正的存储器地址 的位于虚拟地址。

    Memory system and organization for host computer
    5.
    发明公开
    Memory system and organization for host computer 失效
    Speechersystem和组织fürArbeitsrechner。

    公开(公告)号：EP0080877A2

    公开(公告)日：1983-06-08

    申请号：EP82306314.4

    申请日：1982-11-26

    申请人： STORAGE TECHNOLOGY CORPORATION

    发明人： Coulson, Richard L. ,  Blickenstaff, Ronald L. ,  Dodd, David P. ,  Moreno, Robert J. ,  Kinard, Dean P.

    IPC分类号： G11C9/06

    CPC分类号： G06F12/0866 ,  G06F2212/312 ,  G06F2212/601 ,  Y10S707/99956

    摘要： A host computer (10) is backed up by magnetic disk stores (14) which may be of different types having different track lengths. The host computer is conventionally coupled tothe disk stores by channels (12), a storage director (16) and disk control modules (18). A solid-state cache memory array (22) with an associated cache manager (22) are connected to the storage director for storing tracks of data likely to be required by the host computer. In order to provide efficient utilisation of the cache memory array (22) it is arranged in domains having a length which is substantially an integral multiple of all the different track lengths. The domains are assigned to the different classes of disk storage devices (14) and reallocation is effected from time to time on the basis of actual usage.

    摘要翻译： 主计算机（10）由可能具有不同类型的磁盘存储（14）备份，具有不同的磁道长度。 通常，主计算机通过通道（12），存储引导器（16）和盘控制模块（18）耦合到磁盘存储器。 具有相关联的高速缓存管理器（22）的固态高速缓冲存储器阵列（22）连接到存储引导器，用于存储主计算机可能需要的数据的轨道。 为了提供对高速缓冲存储器阵列（22）的有效利用，它被布置在具有基本上是所有不同轨道长度的整数倍的长度的域中。将域分配给不同类别的盘存储设备（14） 并根据实际使用情况不时进行重新分配。

    MEMORY SYSTEM FOR A DATA PROCESSING SYSTEM.
    6.
    发明公开
    MEMORY SYSTEM FOR A DATA PROCESSING SYSTEM. 失效
    存储系统的数据处理系统。

    公开(公告)号：EP0022814A4

    公开(公告)日：1983-01-31

    申请号：EP80900180

    申请日：1980-07-14

    申请人： NCR CORP

    发明人： PATEL NARENDRA MADHAV

    IPC分类号： G11C11/34 ,  G06F12/08 ,  G06F13/00 ,  G11C19/00 ,  G11C7/00 ,  G11C9/06 ,  G11C13/00

    CPC分类号： G06F12/0864

    摘要： A memory system comprises a pair of RAM buffer memories (22, 24) coupled to a CCD main memory (20) to provide high-speed memory access to the memory by a processing means. Each buffer memory has stored therein a page of data transferred from the CCD main memory. Comparison means (76, 78) included in the system compares the page address in a memory request with the page address, located in address registers, of the data stored in the buffer memories. If a comparison is found, the designated buffer memory is accessed for a read/write operation at the addressed memory location. If no comparison is found, circuits (72, 92, 134) using the requested page address transfer the page in which the requested address is located from the CCD main memory to a RAM buffer memory for access by the processing means; the buffer memory to which the page is transferred is the buffer memory that was not accessed in the immediately preceding memory request. If a write operation had occured on a page stored in the buffer memories, the altered page is transferred back to the CCD main memory before a new page of data is transferred to the buffer memory.