公开(公告)号：EP4513542A1

公开(公告)日：2025-02-26

申请号：EP24163892.3

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： PARK, Jisoo ,  KANG, Byungju ,  LIM, Jaehyoung ,  CHUN, Kwanyoung ,  CHOI, Subin

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L29/417 ,  H01L29/775

Abstract: A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.