公开(公告)号：EP4407670A1

公开(公告)日：2024-07-31

申请号：EP23197091.4

申请日：2023-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： PARK, Jisoo ,  HWANG, Donghoon ,  HWANG, Inchan ,  KIM, Hyojin ,  LIM, Jaehyoung

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/8221 ,  H01L27/0688 ,  H01L21/823871 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/42392

Abstract: A 3D stacked FET (100) may include a back-side wiring layer (110) including a first back-side power line (112) and a second back-side power line (114), a first FET (120) on the back-side wiring layer (110), a second FET (130) over the first FET (120), a front-side wiring layer (140) over the second FET (130), a first through-electrode (150) connecting the first FET (120) to the second FET (130),. The front-side wiring layer (140) extends in a first direction and includes a front-side power line (142) connected to the second back-side power line (142) by a second through electrode (160). The first FET (120) and the second FET (130) share a gate (Gc) extending in a second direction perpendicular to the first direction. Each of the first FET (120) and the second FET (130) includes a source (S1, S2) and a drain (D1, D2) respectively on either side of the gate (Gc) in the first direction, and a channel (MBC1, MBC2) between the source and the drain and surrounded by the gate (Gc).

公开(公告)号：EP4513542A1

公开(公告)日：2025-02-26

申请号：EP24163892.3

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： PARK, Jisoo ,  KANG, Byungju ,  LIM, Jaehyoung ,  CHUN, Kwanyoung ,  CHOI, Subin

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L29/417 ,  H01L29/775

Abstract: A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.