公开(公告)号：EP3846223A2

公开(公告)日：2021-07-07

申请号：EP20210064.0

申请日：2020-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHONG, Soogine ,  KIM, Jongseob ,  KIM, Joonyong ,  PARK, Younghwan ,  PARK, Junhyuk ,  SHIN, Dongchul ,  OH, Jaejoon ,  HWANG, Sunkyu ,  HWANG, Injun

IPC: H01L29/778 ,  H01L21/337 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/20

Abstract: A semiconductor device includes a channel layer (110) including a channel; a channel supply layer (120) on the channel layer; a channel separation pattern (200) on the channel supply layer; a gate electrode pattern (310) on the channel separation pattern; and an electric-field relaxation pattern (320) protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.

公开(公告)号：EP4002448A1

公开(公告)日：2022-05-25

申请号：EP21168089.7

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： PARK, Younghwan ,  KIM, Jongseob ,  OH, Jaejoon ,  CHONG, Soogine ,  HWANG, Sunkyu

IPC: H01L23/495 ,  H01L23/31

Abstract: Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

公开(公告)号：EP3846223A3

公开(公告)日：2021-09-15

申请号：EP20210064.0

申请日：2020-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHONG, Soogine ,  KIM, Jongseob ,  KIM, Joonyong ,  PARK, Younghwan ,  PARK, Junhyuk ,  SHIN, Dongchul ,  OH, Jaejoon ,  HWANG, Sunkyu ,  HWANG, Injun

IPC: H01L29/778 ,  H01L21/337 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/20

Abstract: A semiconductor device includes a channel layer (110) including a channel; a channel supply layer (120) on the channel layer; a channel separation pattern (200) on the channel supply layer; a gate electrode pattern (310) on the channel separation pattern; and an electric-field relaxation pattern (320) protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.

公开(公告)号：EP4089732A1

公开(公告)日：2022-11-16

申请号：EP21196944.9

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWANG, Sunkyu ,  KIM, Jongseob ,  KIM, Joonyong ,  PARK, Younghwan ,  PARK, Junhyuk ,  OH, Jaejoon ,  HWANG, Injun

IPC: H01L27/085 ,  H01L29/10 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/098

Abstract: A semiconductor integrated circuit device includes: a channel layer (20); a barrier layer (30); a first p-type semiconductor layer (41) and a second p-type semiconductor layer (42), spaced apart from each other on the barrier layer; and a passivation layer (80) on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer partially inactivates a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

公开(公告)号：EP3902014A1

公开(公告)日：2021-10-27

申请号：EP20195816.2

申请日：2020-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： OH, Jaejoon ,  KIM, Jongseob

IPC: H01L29/778 ,  H01L21/337 ,  H01L29/10 ,  H01L29/20 ,  H01L29/45 ,  H01L29/47

Abstract: Provided are a high electron mobility transistor and a method of manufacturing the high electron mobility transistor. The high electron mobility transistor includes a gate electrode provided on a depletion forming layer (140). The gate electrode includes a first gate electrode (150) configured to form an ohmic contact with the depletion forming layer, and a second gate electrode (160) configured to form a Schottky contact with the depletion forming layer.