MEMORY CONTROLLER, MEMORY DEVICE AND STORAGE DEVICE

    公开(公告)号:EP4040441A2

    公开(公告)日:2022-08-10

    申请号:EP22150726.2

    申请日:2022-01-10

    IPC分类号: G11C29/02

    摘要: A memory device (10) may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device (10) performing a read operation is not corrected. A memory controller (20) may control the memory device (10) to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller (20) may update a table (24), stored in the memory controller (20), using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model (25).

    MEMORY CONTROLLER, MEMORY DEVICE AND STORAGE DEVICE

    公开(公告)号:EP4040441A3

    公开(公告)日:2022-08-17

    申请号:EP22150726.2

    申请日:2022-01-10

    摘要: A memory device (10) may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device (10) performing a read operation is not corrected. A memory controller (20) may control the memory device (10) to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller (20) may update a table (24), stored in the memory controller (20), using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model (25).

    NON-VOLATILE MEMORY DEVICE WITH SELECTION OF ERROR DECODING LEVEL

    公开(公告)号:EP4030434A1

    公开(公告)日:2022-07-20

    申请号:EP21196579.3

    申请日:2021-09-14

    摘要: A controller (400) including a non-volatile memory interface circuit (460) connected to at least one non-volatile memory device (300) and configured to control the at least one non-volatile memory device (300); an error correction circuit (430) configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit (460) according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit (460) is further configured to: receive side information from the at least one non-volatile memory device (300); predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

    STORAGE CONTROLLER
    10.
    发明公开
    STORAGE CONTROLLER 审中-实审

    公开(公告)号:EP4310847A3

    公开(公告)日:2024-03-27

    申请号:EP23163079.9

    申请日:2023-03-21

    IPC分类号: G11C29/02 G11C29/42 G11C29/52

    摘要: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.