摘要:
An electrostatic discharge (ESD) protection circuit (302) in a semiconductor integrated circuit (IC) (100) having protected circuitry. In one embodiment, the ESD protection circuit (302) includes a pad (104), adapted for connection to a protected circuit node of the IC, and an ESD protection device (306), which is coupled between the pad and ground (112). A diode turn-on device (308) is coupled in a forward conduction direction from the pad to a first gate (336) of the ESD protection device. In a second embodiment, the ESD protection circuit (2002) is an SCR having an anode (322) coupled to a first voltage supply line, and a cathode coupled to ground. A parasitic capacitance (2004) is coupled between each the voltage supply line and the grounded cathode.
摘要:
An electrostatic discharge (ESD) protection device (1000), for protecting power lines (1050) of an integrated circuit. In one embodiment, the ESD protection device includes a first silicon controlled rectifier (SCR) (10021) coupled between a first power line (10501) and a second power line(10502), and a second SCR (10022), coupled anti-parallel to the first SCR between the first and second power lines. A first trigger device (10201) is coupled to the first power line and a first trigger gate (10081) of the first SCR, and a second trigger device (10202) coupled to the second power line and a first trigger gate (10082) of the second SCR. The trigger devices and the SCRs provide power-down-mode-compatible operation of the power lines, as well as ESD protection.
摘要:
A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device (100, 200, 300, 400, 500) that can protect very sensitive thin gate oxides by limiting the power dissiptation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment (Figs. 4A and 4B), the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device.
摘要:
An electrostatic discharge (ESD) protection device (102) having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) (100) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) (106) coupled between a protected supply line (104) of the IC and ground (112). A trigger device (1081) is coupled from the supply line to a first gate (136) of the SCR, and a first substrate resistor (130) is coupled between the first gate and ground. A first shunt resistor (1101) is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.