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公开(公告)号：EP0594441B1
公开(公告)日：2002-09-25
申请号：EP93308403.0
申请日：1993-10-21
发明人： Takahashi, Kunihiro , Suzuki, Mizuaki , Yamazaki, Tsuneo , Takasu, Hiroaki , Nakajima, Kunio , Sakurai, Atsushi , Iwaki, Tadao , Kojima, Yoshikazu , Kamiya, Masaaki
CPC分类号： G02F1/13454 , G02F1/133512 , G02F2001/136281 , H01L23/36 , H01L23/367 , H01L27/12 , H01L27/1203 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
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2.发明公开Semi-conductor non-volatile memory and method of writing the same 失效NichtflüchtigerHalbleiterspeicher und Schreibverfahrendafür。
公开(公告)号：EP0387101A2
公开(公告)日：1990-09-12
申请号：EP90302588.0
申请日：1990-03-12
发明人： Hayashi, Yutaka, c/o Agency of Industrial Science , Kojima, Yoshikazu , Takada, Ryoji , Kamiya, Masaaki
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C14/00
摘要： A semi-conductor non-volatile memory comprises one or more integrated memory cells. The or each memory cell comprises a first semi-conductor region (101) having a first surface, an electric charge storage structure (104) disposed on the first surface of the first semi-conductor region for storing electric charge, and a first gate (106) provided to electrically connect to the electric charge storage structure. A second semi-conductor region (121) is electrically connected at one side to the first semi-conductor region (101) and has a second surface. A second gate (126) controls the second surface. A third region (122) is electrically connected to the other side of the second semi-conductor region and a random access potential setting means (131 - 133, 135, 136) is connected to the second gate (126) for setting a potential thereof on a random access basis.
摘要翻译： 半导体非易失性存储器包括一个或多个集成存储器单元。 该存储单元或每个存储单元包括具有第一表面的第一半导体区域（101），设置在用于存储电荷的第一半导体区域的第一表面上的电荷存储结构（104），以及第一栅极 106）被提供以电连接到电荷存储结构。 第二半导体区域（121）在一侧电连接到第一半导体区域（101）并且具有第二表面。 第二门（126）控制第二表面。 第三区域（122）电连接到第二半导体区域的另一侧，并且随机存取电位设置装置（131-133,135,136）连接到第二栅极（126），用于设置其电位 在随机访问的基础上。
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公开(公告)号：EP0387102A3
公开(公告)日：1992-07-15
申请号：EP90302589.8
申请日：1990-03-12
发明人： Hayashi, Yutaka, c/o Agency of Industrial Science , Kojima, Yoshikazu , Takada, Ryoji , Kamiya, Masaaki
CPC分类号： H01L29/7883 , G11C14/00
摘要： A semi-conductor non-volatile memory comprises one or more integrated memory cells. Each memory cell comprises a first semi-conductor region having a first surface, and electric charge storage structure (5) disposed on the first surface for storing electric charge and a first gate (7) electrically coupled to the electric charge storage structure. There is a second region electrically connected to the first surface and a second gate (9) electrically coupled to either the electric charge storage structure or the first gate. A random access potential setting means (9 - 11) sets a random access potential to the first gate (7).
摘要翻译： 半导体非易失性存储器包括一个或多个集成存储器单元。 每个存储单元包括具有第一表面的第一半导体区域和设置在用于存储电荷的第一表面上的电荷存储结构（5）和电耦合到电荷存储结构的第一栅极（7）。 电连接到第一表面的第二区域和电耦合到电荷存储结构或第一栅极的第二栅极（9）。 随机存取电位设置装置（9-11）将随机存取电位设置到第一门（7）。
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公开(公告)号：EP0237280A3
公开(公告)日：1989-04-12
申请号：EP87301930.1
申请日：1987-03-05
CPC分类号： H01L43/065
摘要： A magnetic sensor comprising at least one Hall device (1,2) which is formed on the crystal surface (100) of a silicon single crystal chip (0), characterised in that the or each Hall device (1,2) is arranged so that the direction of current flow between its electrodes (101,102 or 201,202) is substantially parallel to the direction 100 or the direction 010 on the crystal surface (100).
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5.发明公开Semiconductor non-volatile random access memory 失效Nicht-flüchtigerDirektzugriffshalbleiterspeicher。
公开(公告)号：EP0259158A2
公开(公告)日：1988-03-09
申请号：EP87307778.8
申请日：1987-09-03
申请人： AGENCY OF INDUSTRIAL SCIENCE & TECHNOLOGY MINISTRY OF INTERNATIONAL TRADE & INDUSTRY , SEIKO INSTRUMENTS INC.
IPC分类号： G11C11/00
CPC分类号： G11C14/00
摘要： A semiconductor non-volatile random access memory comprises an insulating film (12) disposed on a semiconductor substrate (100) of a first conductivity type. Charge storing means (13) are provided in the insulating film. A first insulated gate electrode (15) is electrically coupled to the charge storing means (13) and controls electric potential in a region (11) in the surface of the substrate under the charge storing means. A second insulated gate electrode (35) is provided to form a channel (31) in a region of the substrate (100) adjacent to the region (11) under the charge storing means (13). A read/write region (40) is of a second conductivity type opposite the first conductivity type provided adjacent to the region where the channel (31) is formed. In operation, volatile information in the form of electric potential or electric charge is stored when power is supplied to the region (11) in the substrate under the charge storing means (13), and information is transferred to the charge storing means (13) to store the information therein in non-volatile form before a power supply is perfectly turned off.
摘要翻译： 半导体非易失性随机存取存储器包括设置在第一导电类型的半导体衬底（100）上的绝缘膜（12）。 电荷存储装置（13）设置在绝缘膜中。 第一绝缘栅电极（15）电耦合到电荷存储装置（13），并控制在电荷存储装置下的衬底表面中的区域（11）中的电位。 提供第二绝缘栅电极（35）以在与电荷存储装置（13）下方的区域（11）相邻的基板（100）的区域中形成通道（31）。 读/写区域（40）具有与形成通道（31）的区域相邻提供的与第一导电类型相反的第二导电类型。 在操作中，当向电荷存储装置（13）下方的基板中的区域（11）供电时，存储电势或电荷形式的挥发性信息，并将信息传送到电荷存储装置（13） 在电源完全关闭之前以非易失性形式存储信息。
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公开(公告)号：EP0952611A3
公开(公告)日：2000-06-28
申请号：EP99202202.0
申请日：1993-10-21
发明人： Takahashi, Kunihiro , Suzuki, Mizuaki , Yamazaki, Tsuneo , Takasu, Hiroaki , Nakajima, Kunio , Sakurai, Atsushi , Iwaki, Tadao , Kojima, Yoshikazu , Kamiya, Masaaki
CPC分类号： G02F1/13454 , G02F1/133512 , G02F2001/136281 , H01L23/36 , H01L23/367 , H01L27/12 , H01L27/1203 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor substrate and a light-valve semiconductor substrate is provided so as to prevent the threshold value of a MOS transistor on a single-crystal silicon device forming layer from increasing in order to obtain a MOS integrated circuit with a high reliability even for over a long time of operation. A semiconductor substrate and a light-valve semiconductor substrate comprising a single-crystal silicon thin-film device forming layer 5001 formed above an insulating substrate 5004 through an adhesive layer 5003 and an insulating layer 5002 formed on the single-crystal silicon thin-film device forming layer, wherein heat conductive layers 5201 and 5202 made of a material with a high heat conductivity are arranged between the single-crystal silicon thin-film device forming layer and the adhesive layer and on the insulating layer.
摘要翻译： 提供半导体衬底和光阀半导体衬底以防止单晶硅器件形成层上的MOS晶体管的阈值增加，以便获得即使对于超过一个晶体管也具有高可靠性的MOS集成电路 操作时间长。 半导体衬底和光阀半导体衬底包括通过粘合层5003形成在绝缘衬底5004上方的单晶硅薄膜器件形成层5001和形成在单晶硅薄膜器件上的绝缘层5002 其中在单晶硅薄膜器件形成层和粘合剂层之间以及绝缘层上布置有由具有高导热率的材料制成的导热层5201和5202。
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公开(公告)号：EP0952611A2
公开(公告)日：1999-10-27
申请号：EP99202202.0
申请日：1993-10-21
发明人： Takahashi, Kunihiro , Suzuki, Mizuaki , Yamazaki, Tsuneo , Takasu, Hiroaki , Nakajima, Kunio , Sakurai, Atsushi , Iwaki, Tadao , Kojima, Yoshikazu , Kamiya, Masaaki
CPC分类号： G02F1/13454 , G02F1/133512 , G02F2001/136281 , H01L23/36 , H01L23/367 , H01L27/12 , H01L27/1203 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor substrate and a light-valve semiconductor substrate is provided so as to prevent the threshold value of a MOS transistor on a single-crystal silicon device forming layer from increasing in order to obtain a MOS integrated circuit with a high reliability even for over a long time of operation. A semiconductor substrate and a light-valve semiconductor substrate comprising a single-crystal silicon thin-film device forming layer 5001 formed above an insulating substrate 5004 through an adhesive layer 5003 and an insulating layer 5002 formed on the single-crystal silicon thin-film device forming layer, wherein heat conductive layers 5201 and 5202 made of a material with a high heat conductivity are arranged between the single-crystal silicon thin-film device forming layer and the adhesive layer and on the insulating layer.
摘要翻译： 提供了一种半导体衬底和光阀半导体衬底，以便防止单晶硅器件形成层上的MOS晶体管的阈值增加，以便获得具有高可靠性的MOS集成电路，即使在超过 操作时间长 一种半导体衬底和一个光阀半导体衬底，它包括通过粘合剂层5003形成在绝缘衬底5004上的单晶硅薄膜器件形成层5001和形成在单晶硅薄膜器件上的绝缘层5002 形成层，其中由单个硅薄膜器件形成层和粘合剂层之间以及绝缘层上设置由具有高导热性的材料制成的导热层5201和5202。
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公开(公告)号：EP0237280A2
公开(公告)日：1987-09-16
申请号：EP87301930.1
申请日：1987-03-05
CPC分类号： H01L43/065
摘要： A magnetic sensor comprising at least one Hall device (1,2) which is formed on the crystal surface (100) of a silicon single crystal chip (0), characterised in that the or each Hall device (1,2) is arranged so that the direction of current flow between its electrodes (101,102 or 201,202) is substantially parallel to the direction 100 or the direction 010 on the crystal surface (100).
摘要翻译： 一种磁传感器，包括形成在单晶硅片（0）的晶体表面（100）上的至少一个霍尔器件（1,2），其特征在于，所述霍尔器件（1,2）被布置成 其电极（101,102或201,202）之间的电流流动方向基本上平行于晶体表面（100）上的方向@ 00或方向010。
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公开(公告)号：EP0474474A3
公开(公告)日：1992-09-30
申请号：EP91308095.8
申请日：1991-09-04
发明人： Takasu, Hiroaki , Kojima, Yoshikazu , Kamiya, Masaaki , Yamazaki, Tsuneo , Suzuki, Hiroshi , Taguchi, Masaaki , Takano, Ryuichi , Yabe, Satoru
IPC分类号： G02F1/136 , H01L27/12 , G02F1/1337
CPC分类号： H01L27/1251 , G02F1/13378 , G02F1/13454 , G02F1/136213 , G02F2202/105 , G09G3/3648 , G09G5/006 , G09G2330/02 , H01L27/1214
摘要： The invention provides a semi-conductor light valve device and a process for fabricating the same. The device comprises an insulating substrate (7) having a semi-conductor single crystal thin film (1) over at least a portion thereof and providing a pixel array region and a peripheral circuit region. The pixel array region includes a plurality of switch elements (2) for selectively energising a plurality of pixel electrodes (3), and the peripheral circuit region includes drive circuits (15, 16) for operating the switch elements. At least circuit elements of the drive circuits are formed from the semi-conductor single crystal thin film. In the fabricating process, the semi-conductor single crystal thin film and the insulating substrate are formed as a composite substrate by adhering a semiconductor single crystal plate to the surface of the insulating substrate and by polishing the single crystal plate. The circuit elements of the drive circuits are then formed by treating the single crystal plate.
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公开(公告)号：EP0387101A3
公开(公告)日：1992-07-22
申请号：EP90302588.0
申请日：1990-03-12
发明人： Hayashi, Yutaka, c/o Agency of Industrial Science , Kojima, Yoshikazu , Takada, Ryoji , Kamiya, Masaaki
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C14/00
摘要： A semi-conductor non-volatile memory comprises one or more integrated memory cells. The or each memory cell comprises a first semi-conductor region (101) having a first surface, an electric charge storage structure (104) disposed on the first surface of the first semi-conductor region for storing electric charge, and a first gate (106) provided to electrically connect to the electric charge storage structure. A second semi-conductor region (121) is electrically connected at one side to the first semi-conductor region (101) and has a second surface. A second gate (126) controls the second surface. A third region (122) is electrically connected to the other side of the second semi-conductor region and a random access potential setting means (131 - 133, 135, 136) is connected to the second gate (126) for setting a potential thereof on a random access basis.
摘要翻译： 半导体非易失性存储器包括一个或多个集成存储器单元。 该存储单元或每个存储单元包括具有第一表面的第一半导体区域（101），设置在用于存储电荷的第一半导体区域的第一表面上的电荷存储结构（104），以及第一栅极 106）被提供以电连接到电荷存储结构。 第二半导体区域（121）在一侧电连接到第一半导体区域（101）并且具有第二表面。 第二门（126）控制第二表面。 第三区域（122）电连接到第二半导体区域的另一侧，并且随机存取电位设置装置（131-133,135,136）连接到第二栅极（126），用于设置其电位 在随机访问的基础上。
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