COMPACT EFUSE ARRAY WITH DIFFERENT MOS SIZES ACCORDING TO PHYSICAL LOCATION IN A WORD LINE
    1.
    发明公开
    COMPACT EFUSE ARRAY WITH DIFFERENT MOS SIZES ACCORDING TO PHYSICAL LOCATION IN A WORD LINE 审中-公开
    根据字线中的物理位置,具有不同MOS尺寸的紧凑型EFUSE阵列

    公开(公告)号:EP3188189A1

    公开(公告)日:2017-07-05

    申请号:EP16204643.7

    申请日:2016-12-16

    发明人: YANG, Chia Chi

    IPC分类号: G11C17/16 G11C17/18

    CPC分类号: G11C17/16 G11C17/18

    摘要: A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.

    摘要翻译: 电可编程熔丝(eFuse)单元阵列包括至少一个连接两个相邻eFuse单元的连接开关。 每个eFuse单元包括eFuse,用于通过写入电流的第一部分的写入开关,用于通过写入电流的第二部分或读取电流的读取/写入开关以及公共节点。 eFuse,写入开关,读取/写入开关以及至少一个连接开关在公共节点处彼此连接。 通过打开和关闭至少一个连接开关,电流在eFuse单元之间分开,从而可以减小写入开关的尺寸,从而减小阵列的总面积。

    A BANDGAP WITH SYSTEM SLEEP MODE
    2.
    发明公开
    A BANDGAP WITH SYSTEM SLEEP MODE 审中-公开
    系统休眠模式的带宽

    公开(公告)号:EP3301606A1

    公开(公告)日:2018-04-04

    申请号:EP17192400.4

    申请日:2017-09-21

    IPC分类号: G06F21/81 G05F3/30

    摘要: A method operates a bandgap voltage reference circuit that includes a bias circuit for receiving a feedback signal and outputting a bias signal, an amplifier for receiving the bias signal and outputting a first reference signal as the feedback signal, an output circuit for receiving the first reference signal and outputting a second reference signal, and an output switch for outputting the second reference signal as an output signal. The method includes, after powering up the bandgap voltage reference circuit, determining whether the output signal is stable, when the output signal is stable, turning off the output switch; turning off the bias circuit; and turning off the output circuit. The sequential turning off the output switch, the output circuit, and the bias circuit puts the bandgap voltage reference circuit into a sleep mode to save power.

    摘要翻译: 一种方法操作带隙电压参考电路,该电路包括用于接收反馈信号并输出​​偏置信号的偏置电路,用于接收偏置信号并输出​​第一参考信号作为反馈信号的放大器,用于接收第一参考的输出电路 信号并输出​​第二参考信号;以及输出开关,用于输出第二参考信号作为输出信号。 该方法包括:在给带隙电压基准电路通电之后,确定输出信号是否稳定,当输出信号稳定时,关闭输出开关; 关闭偏置电路; 并关闭输出电路。 依次关闭输出开关,输出电路和偏置电路使带隙电压基准电路进入睡眠模式以节省功耗。

    BANDGAP REFERENCE CIRCUIT AND METHOD OF USING THE SAME
    3.
    发明公开
    BANDGAP REFERENCE CIRCUIT AND METHOD OF USING THE SAME 审中-公开
    BANDGAP参考电路及其使用方法

    公开(公告)号:EP3318950A1

    公开(公告)日:2018-05-09

    申请号:EP17199817.2

    申请日:2017-11-03

    IPC分类号: G05F3/30 H03K19/00

    摘要: A bandgap reference circuit and method of using the same are provided. The bandgap reference circuit includes a startup component; an output component; and a bandgap core component coupled there-between. The bandgap core component includes a reference point having a voltage associated with an output signal of the output component. A controller is configured for controlling the bandgap core component and the output component to switch between a low power consumption mode and a normal operation mode based on the voltage at the reference point. When the bandgap core component and the output component operate in the normal operation mode, the bandgap reference circuit outputs a stable voltage and has a first power consumption. When the bandgap core component and the output component operate in the low power consumption mode, the bandgap reference circuit has a second power consumption less than the first power consumption.

    摘要翻译: 提供一种带隙参考电路及其使用方法。 带隙基准电路包括启动组件; 输出组件; 以及耦合在其间的带隙核心组件。 带隙核心组件包括具有与输出组件的输出信号相关联的电压的参考点。 控制器被配置用于基于参考点处的电压来控制带隙核心组件和输出组件以在低功耗模式和正常操作模式之间切换。 当带隙核心组件和输出组件以正常操作模式操作时,带隙参考电路输出稳定的电压并且具有第一功耗。 当带隙核心组件和输出组件以低功耗模式操作时,带隙基准电路具有小于第一功耗的第二功耗。