-
1.发明公开
公开(公告)号：EP1166180A1
公开(公告)日：2002-01-02
申请号：EP00918219.7
申请日：2000-03-21
发明人： SAVAGE, Richard, N. , MENAGH, Frank, S. , CARVALHEIRA, Helder, R. , TROIANI, Philip, A. , COSSENTINE, Dan, L. , VAUGHAN, Eric, R. , MAYER, Bruce, E.
CPC分类号： H01L21/68707 , C23C16/54 , H01L21/67173 , H01L21/67178 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67742 , H01L21/67745 , H01L21/67751 , Y10S414/141
摘要： A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.
摘要翻译： 一种半导体晶片处理系统，包括具有垂直堆叠的半导体晶片处理室的多室模块和专用于每个半导体晶片处理室的负载锁定室。 每个处理室包括用于在晶片处理期间保持晶片的卡盘。 多室模块可以以线性阵列取向。 该系统还包括具有双晶片单轴传送臂的装置，该双晶片单轴传送臂包括围绕单个枢轴枢转地安装在所述加载锁定室内的单体臂。 该装置适于在负载锁定腔室和处理腔室之间同时承载两个晶片，一个未加工和一个处理。 还提供了利用所公开的系统的方法。
-
2.发明授权SEMICONDUCTOR WAFER PROCESSING SYSTEM WITH VERTICALLY-STACKED PROCESS CHAMBERS AND SINGLE-AXIS DUAL-WAFER TRANSFER SYSTEM 有权半导体晶片ETWICKLUNGSGERÄT垂直和GESTAPELTEENTWICKLUNGSRAÜME单轴双晶片传送系统
公开(公告)号：EP1166180B1
公开(公告)日：2005-11-30
申请号：EP00918219.7
申请日：2000-03-21
发明人： SAVAGE, Richard, N. , MENAGH, Frank, S. , CARVALHEIRA, Helder, R. , TROIANI, Philip, A. , COSSENTINE, Dan, L. , VAUGHAN,Eric R. , MAYER, Bruce, E.
CPC分类号： H01L21/68707 , C23C16/54 , H01L21/67173 , H01L21/67178 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67742 , H01L21/67745 , H01L21/67751 , Y10S414/141
摘要： A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.
-
搜索结果
2 条记录 (耗时 0.01 秒)
