公开(公告)号：EP3490003A1

公开(公告)日：2019-05-29

申请号：EP17831086.8

申请日：2017-07-20

申请人： Sony Corporation ,  Sony Semiconductor Solutions Corporation

发明人： HIROSE, Yohei ,  YAGI, Iwao ,  HIRATA, Shintarou ,  MOGI, Hideaki ,  BANDO, Masashi ,  ENOKI, Osamu

IPC分类号： H01L27/30 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/146 ,  H01L31/10 ,  H01L51/42 ,  H04N5/369

摘要： [Solving Means]
A first solid-state imaging element according to an embodiment of the present disclosure includes a bottom-electrode; a top-electrode opposed to the bottom-electrode; a photoelectric conversion layer provided between the bottom-electrode and the top-electrode and including a first organic semiconductor material; and an upper inter-layer provided between the top-electrode and the photoelectric conversion layer, and including a second organic semiconductor material having a halogen atom in a molecule at a concentration in a range from 0 volume % or more to less than 0.05 volume %.

公开(公告)号：EP4412238A1

公开(公告)日：2024-08-07

申请号：EP22872986.9

申请日：2022-09-22

申请人： Sony Semiconductor Solutions Corporation

发明人： KUMAGAI, Yoshimichi ,  BANDO, Masashi ,  OSAWA, Naoyuki ,  AKIYAMA, Shunya ,  SHIRAKATA, Toru ,  ABE, Takashi ,  AOTA, Tomoya

IPC分类号： H04N25/76 ,  H01L27/146

CPC分类号： H01L27/146 ,  H04N25/76

摘要： A pixel layout is optimized. An amplification unit generates a signal corresponding to a charge held in a charge holding unit and outputs the signal to a predetermined first output node. A first capacitive element has one end connected to the first output node and holds a reset level that is a level of the signal at the time of resetting by a first reset unit. A second capacitive element has one end connected to the first output node and holds an image signal level that is a level of the signal when the charge is transferred to the charge holding unit. A readout circuit is connected to a second output node, reads each of the reset level held in the first capacitive element and the image signal level held in the second capacitive element, and outputs the reset level and the image signal level as a reset signal and an image signal, respectively.

公开(公告)号：EP4261890A1

公开(公告)日：2023-10-18

申请号：EP21903196.0

申请日：2021-11-25

申请人： Sony Semiconductor Solutions Corporation

发明人： BANDO, Masashi

IPC分类号： H01L27/146 ,  H04N5/355 ,  H04N5/3745

摘要： A solid-state imaging element according to an aspect of the present disclosure includes: a first photoelectric conversion unit (31) having a light incident surface on which light is incident; a first gate electrode (36) provided in the first photoelectric conversion unit (31) via an insulating film (35); a second photoelectric conversion unit (32) provided on a side of the light incident surface with respect to the first photoelectric conversion unit (31); and a voltage application unit that applies a voltage corresponding to the number of charges accumulated by the second photoelectric conversion unit (32) to the first gate electrode (36).

公开(公告)号：EP4160685A1

公开(公告)日：2023-04-05

申请号：EP21812547.4

申请日：2021-04-07

申请人： Sony Semiconductor Solutions Corporation

发明人： YOSHITA, Ryoto ,  KUMAGAI, Yoshimichi ,  OSAWA, Naoyuki ,  NAGATA, Kengo ,  BANDO, Masashi

IPC分类号： H01L27/146 ,  H04N5/369

摘要： An imaging element according to an embodiment of the present disclosure includes: a semiconductor substrate; a multilayer wiring layer; a plurality of structures; and a light reflecting layer. The semiconductor substrate has a first surface and a second surface. The first surface serves as a light incidence surface. The second surface is opposite to the first surface. The semiconductor substrate includes a light receiving section for each of pixels. The light receiving section generates electric charge through photoelectric conversion. The electric charge corresponds to an amount of received light. The multilayer wiring layer is provided on the second surface side of the semiconductor substrate. The multilayer wiring layer has a plurality of wiring layers stacked therein with an interlayer insulating layer interposed in between. The plurality of structures is provided on the second surface of the semiconductor substrate in the multilayer wiring layer. The light reflecting layer is provided in the multilayer wiring layer. The light reflecting layer forms a reflective region or a non-reflective region in a region with the interlayer insulating layer interposed in between. The region has none of the structures formed therein. The reflective region is substantially symmetrical with respect to an optical center of the pixel. The non-reflective region is substantially symmetrical with respect to the optical center of the pixel.