公开(公告)号：EP4443509A1

公开(公告)日：2024-10-09

申请号：EP22901158.0

申请日：2022-11-22

Applicant: Sony Semiconductor Solutions Corporation

Inventor： TOGASHI, Hideaki ,  OHKUBO, Tomohiro ,  KAWAI, Nobuhiro ,  TSUNO, Hitoshi ,  TAMURA, Syuto ,  TAKADA, Tetsuro

IPC: H01L27/146

CPC classification number: H01L27/146

Abstract: A photodetection device according to an embodiment includes a plurality of pixels arranged in a matrix, in which each of the pixels includes a semiconductor substrate having a first surface and a second surface opposed to each other, a first photoelectric conversion portion disposed on the second surface side of the semiconductor substrate, an insulating layer covering the first surface of the semiconductor substrate, and at least one pixel transistor located on the first surface side of the semiconductor substrate with the insulating layer interposed therebetween.

公开(公告)号：EP3734659B1

公开(公告)日：2024-09-11

申请号：EP18895966.2

申请日：2018-12-12

IPC: H01L27/146 ,  H01L31/10 ,  H04N5/33

CPC classification number: H01L27/146 ,  H01L31/10 ,  H01L27/14636 ,  H01L27/14623 ,  H01L27/14605 ,  H01L27/14692 ,  H01L27/14665 ,  H04N25/70

公开(公告)号：EP4425535A1

公开(公告)日：2024-09-04

申请号：EP22886565.5

申请日：2022-09-28

Applicant: Sony Semiconductor Solutions Corporation

Inventor： HATANO, Keisuke

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/146

CPC classification number: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/146

Abstract: To provide a semiconductor device, a manufacturing method therefor, and an electronic apparatus that can be applied to a chip-scale package-type solid-state imaging device that reduces a parasitic capacitance generated between an internal electrode and a board silicon so as to suppress waveform distortion and signal delay of high-frequency signals, thereby enabling a high-speed operation. A configuration to include: a board silicon; a silicon oxide film stacked on the board silicon; an inter-wiring-layer film having an internal electrode stacked on the silicon oxide film; a through-hole forming a stepped hole with a larger-diameter hole extending from the board silicon to the silicon oxide film and a smaller-diameter hole extending from the silicon oxide film to the internal electrode; an interlayer dielectric film stacked on a circumferential side surface of the larger-diameter hole and the board silicon; and a redistribution layer formed on an inner peripheral surface of the through-hole and the interlayer dielectric film and connected to the internal electrode is employed.

公开(公告)号：EP4425225A1

公开(公告)日：2024-09-04

申请号：EP22886820.4

申请日：2022-10-19

Applicant: Kyocera Corporation

Inventor： MAEDA, Junki

IPC: G02B5/00 ,  H01L27/146

CPC classification number: H01L27/146 ,  G02B5/00

Abstract: A light shielding film includes: a first surface; and a second surface opposite to the first surface. The light shielding film contains resin, carbon black, and first-type graphite fillers, and longitudinal directions of the first-type graphite fillers are substantially parallel to at least one surface of the first surface and the second surface in a longitudinal section.

公开(公告)号：EP3913908B1

公开(公告)日：2024-08-21

申请号：EP21180574.2

申请日：2017-04-03

IPC: H01L27/146

CPC classification number: H01L27/146 ,  H01L27/14609 ,  H04N25/76 ,  H04N25/40

公开(公告)号：EP4415376A1

公开(公告)日：2024-08-14

申请号：EP22878426.0

申请日：2022-09-29

Applicant: Sony Semiconductor Solutions Corporation

Inventor： TSUKUDA, Yasunori ,  SHIMADA, Shohei ,  BAINES, Yannick ,  MATSUNUMA, Takeshi

IPC: H04N25/70 ,  G01J1/42 ,  G01J1/44 ,  G01S7/4861 ,  G01S17/89 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/146 ,  H01L31/10 ,  H01L31/107 ,  H01L31/12

CPC classification number: G01J1/44 ,  G01J1/42 ,  G01S7/4861 ,  G01S17/89 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/146 ,  H01L31/10 ,  H01L31/107 ,  H01L31/12 ,  H04N25/70

Abstract: [Object]
A bias voltage of a photoelectric conversion element is accurately adjustable regardless of a quantity of incident light.
[Solving Means]
An optical detection device includes a first pixel that has a photoelectric conversion element for generating a carrier by photoelectric conversion, a second pixel that has a carrier generation unit for generating a carrier by a cause other than photoelectric conversion, and a control circuit that controls a bias voltage applied to each of the photoelectric conversion element and the carrier generation unit, according to the carrier generated by the second pixel. The photoelectric conversion element includes a first photoelectric conversion region in which photoelectric conversion is possible and a first pinning film disposed at a position in contact with the first photoelectric conversion region. The carrier generation unit includes a second photoelectric conversion region in which photoelectric conversion is possible, and includes a second pinning film that is partially removed, at a position in contact with the second photoelectric conversion region, or no member that reduces dark current, in an entire area of the second photoelectric conversion region.

公开(公告)号：EP4391575A1

公开(公告)日：2024-06-26

申请号：EP22858194.8

申请日：2022-07-06

Applicant: Sony Semiconductor Solutions Corporation

Inventor： YUFUNE, Shuta

IPC: H04N25/70 ,  G03B15/00 ,  H01L27/146 ,  H04N23/00 ,  H04N23/60 ,  H04N25/76 ,  H04N23/12

CPC classification number: G03B15/00 ,  H01L27/146

Abstract: A resolution of an image of a subject is adjusted. An imaging device includes an imaging element, a resolution selection unit, and an image signal addition unit. In the imaging element, pixel blocks are arranged in a two-dimensional matrix. The pixel blocks include a plurality of pixels and an on-chip lens. The plurality of pixels performs photoelectric conversion on incident light from a subject, and generates an image signal. The on-chip lens is arranged in common in the plurality of pixels, and collects the incident light on the plurality of pixels. The resolution selection unit selects a first resolution, a second resolution, and a third resolution. The first resolution is in accordance with the size of the pixels. The second resolution is in accordance with the size of the pixel blocks. The third resolution is in accordance with the size of a pixel block unit including a plurality of adjacent pixel blocks. The image signal addition unit generates a second image signal by adding the generated image signals in accordance with the selected resolution.

公开(公告)号：EP4386848A1

公开(公告)日：2024-06-19

申请号：EP22855900.1

申请日：2022-08-10

Applicant: Sony Semiconductor Solutions Corporation

Inventor： GOI, Kazuhiro

IPC: H01L27/146 ,  G02B3/02 ,  H04N25/70

CPC classification number: H04N25/70 ,  H01L27/146 ,  G02B3/02

Abstract: An imaging apparatus that reduces the influence of light condensing shift is provided even in a case where the position of the on-chip lens of pixels or the like varies. The imaging apparatus according to the present disclosure includes a plurality of pixels and an on-chip lens. The pixel included in the imaging apparatus performs photoelectric conversion of incident light from a subject to generate an image signal. The on-chip lens included in the imaging apparatus is arranged in common in the plurality of pixels, includes the non-condensing region in the central portion, and condenses the incident light on the plurality of pixels in the peripheral portion.

公开(公告)号：EP4350772A3

公开(公告)日：2024-06-05

申请号：EP24158837.5

申请日：2018-06-08

Applicant: Sony Semiconductor Solutions Corporation

Inventor： KAWAI, Nobuhiro ,  TOGASHI, Hideaki ,  KOGA, Fumihiko ,  YAMAGUCHI, Tetsuji ,  HIRATA, Shintarou ,  WATANABE, Taiichiro ,  ANDO, Yoshihiro

IPC: H01L27/146 ,  H04N25/76

CPC classification number: H01L27/146 ,  H01L27/14627 ,  H01L27/14647 ,  H01L27/14665 ,  H01L27/14612 ,  H01L27/14603 ,  H01L27/14638 ,  H01L27/14641 ,  H01L27/1462 ,  H04N25/76 ,  H10K39/00

Abstract: A solid-state imaging element includes a pixel including a first imaging element, a second imaging element, a third imaging element, and an on-chip micro lens 90. The first imaging element includes a first electrode 11, a third electrode 12, and a second electrode 16. The pixel further includes a third electrode control line VOA connected to the third electrode 12 and a plurality of control lines 62B connected to various transistors included in the second and third imaging elements and different from the third electrode control line VOA. In the pixel, a distance between the center of the on-chip micro lens 90 included in the pixel and any one of the plurality of control lines 62B included in the pixel is shorter than a distance between the center of the on-chip micro lens 90 included in the pixel and the third electrode control line VOA included in the pixel.

公开(公告)号：EP4376082A1

公开(公告)日：2024-05-29

申请号：EP22845596.0

申请日：2022-02-21

Applicant: Sony Semiconductor Solutions Corporation

Inventor： MITARAI, Shun

IPC: H01L27/146 ,  H01L23/02 ,  H01L23/10 ,  H01L23/12

CPC classification number: H01L27/146 ,  H01L23/02 ,  H01L23/12 ,  H01L23/10

Abstract: Provided is a semiconductor package further reduced in size.
A semiconductor package, including a mounting substrate; a semiconductor chip having a smaller area than the mounting substrate and mounted on a main surface of the mounting substrate; a sealing glass facing the semiconductor chip and the mounting substrate, connected to the mounting substrate by a substrate connection part, and connected to the semiconductor chip by a chip connection part; and a connection wiring layer provided on a first surface of the sealing glass that faces the mounting substrate and the semiconductor chip, and electrically connected to the mounting substrate and the semiconductor chip via the substrate connection part and the chip connection part, wherein the mounting substrate, the semiconductor chip, and the sealing glass have approximately the same thermal expansion coefficient.