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    Method and apparatus for cycle-based computation
    1.
    发明公开
    Method and apparatus for cycle-based computation 审中-公开
    Verfahren undGerätfürzyklusbasierte Berechnungen

    公开(公告)号：EP1291791A2

    公开(公告)日：2003-03-12

    申请号：EP02102117.5

    申请日：2002-08-09

    申请人： Sun Microsystems, Inc.

    发明人： McWilliams, Thomas M. ,  Rubin, Jeffrey B. ,  Pappas, Derek E. ,  Olukotun, Oyekunle A. ,  Broughton, Jeffrey M. ,  Emberson, David R. ,  Lam, William Kwei-Cheung ,  Chen, Liang T. ,  Chen, Ihao ,  Cohen, Earl T. ,  Parkin, Michael W.

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F2217/68

    摘要： A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

    摘要翻译： 用于基于周期的计算的计算机系统包括处理器阵列，适于翻译基于周期的设计的翻译组件，可操作地连接到处理器阵列和转换组件的主计算机，将多个成员互连的数据连接组件 使用静态路由的处理器阵列，使处理器阵列的多个成员之间的已知定时关系的同步组件，适于将主服务请求从处理器阵列的成员发送到主计算机的主服务请求组件，以及 访问组件，其适于访问所述处理器阵列的状态的一部分以及所述数据连接状态的一部分。

    Hardware mechanism for optimizing instruction and data prefetching
    2.
    发明公开
    Hardware mechanism for optimizing instruction and data prefetching 失效
    优化Vorausholung命令和数据的硬件配置

    公开(公告)号：EP0810517A3

    公开(公告)日：1999-11-10

    申请号：EP97107455.4

    申请日：1997-05-06

    申请人： SUN MICROSYSTEMS, INC.

    发明人： Emberson, David R.

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F2212/6028

    摘要： Disclosed is a prefetch execution unit, prefetch instruction buffer and a prefetch victim buffer which operate to optimize prefetching by recording a particular cache miss' history. To record cache misses, victimized (overwritten) lines and/or a prefetch tag are stored in a prefetch victim buffer. When the processor experiences a cache miss, it accesses the prefetch victim buffer to retrieve information relating to the prefetch victim. The prefetch execution unit then modifies the values of the additional field or fields and then stores the modified augmented prefetch instruction in the prefetch instruction buffer. The next time a prefetch instruction for the victimized lines is executed by the processor, the new values of the modified augmented prefetch instruction will dictate where the prefetch information is stored or what size increment it has. By continuous modification of the augmented prefetch instructions, eventually thrashing may be eliminated.

    Tunable software control of Harvard architecture cache memories using prefetch instructions
    3.
    发明公开
    Tunable software control of Harvard architecture cache memories using prefetch instructions 失效
    Abstimmbare Softwaresteuerung von Pufferspeichern einer Harvard-Architektur mittels Vorausladebefehlen

    公开(公告)号：EP0752645A2

    公开(公告)日：1997-01-08

    申请号：EP96110744.8

    申请日：1996-07-03

    申请人： SUN MICROSYSTEMS, INC.

    发明人： Emberson, David R.

    IPC分类号： G06F9/38

    CPC分类号： G06F12/0862 ,  G06F9/383 ,  G06F12/0848 ,  G06F2212/6028

    摘要： Disclosed is an instruction-level method and system for prefetching data or instructions of variable size to specified cache sets. A prefetch instruction containing binary fields allows the compiler, loader or runtime software to control cache prefetching and reduce thrashing by providing the prefetch hardware with information as to the optimal cache set location and the optimal amount of data to be prefetched. Support of Harvard architectures with separate instruction and data caches is provided by separate software control of instruction and data caches. The cache set number is identified to indicate into which set the information is to be preloaded. The size field provides a variable prefetch size. An address field indicates the address where prefetching begins.

    摘要翻译： 公开了一种用于将数据或可变大小的指令预取到指定高速缓存组的指令级方法和系统。 包含二进制字段的预取指令允许编译器，加载器或运行时软件通过向预取硬件提供关于最佳高速缓存集位置和要预取的最佳数据量的信息来控制高速缓存预取和减少抖动。 通过单独的指令和数据高速缓存的软件控制来提供具有单独指令和数据高速缓存的哈佛架构的支持。 识别高速缓存组编号以指示信息将被预加载到哪个集合中。 size字段提供可变预取大小。 地址字段指示预取开始的地址。

    Memory management unit incorporating prefetch control
    5.
    发明公开
    Memory management unit incorporating prefetch control 失效
    对于预选控制存储器管理单元

    公开(公告)号：EP0752644A3

    公开(公告)日：2001-08-22

    申请号：EP96110735.6

    申请日：1996-07-03

    申请人： SUN MICROSYSTEMS, INC.

    发明人： Emberson, David R.

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/1027 ,  G06F2212/6028

    摘要： Disclosed is a method and system for providing for the prefetching of data or instructions A prefetch instruction which is in an instruction stream is processed by memory management unit (MMU) where prefetch cache control information is placed as part of the already existing prefetch instruction. Once processed by the MMU, the prefetch instruction thus contains binary fields allowing the operating system or runtime software to control cache prefetching by assigning values to the binary fields which provide the optimal cache set location and the optimal amount of data to be prefetched and thus reduces thrashing.

    Tunable software control of Harvard architecture cache memories using prefetch instructions
    8.
    发明公开
    Tunable software control of Harvard architecture cache memories using prefetch instructions 失效
    由哈佛结构的预取指令缓冲器装置的可调谐软件控制

    公开(公告)号：EP0752645A3

    公开(公告)日：2002-01-02

    申请号：EP96110744.8

    申请日：1996-07-03

    申请人： SUN MICROSYSTEMS, INC.

    发明人： Emberson, David R.

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F12/0862 ,  G06F9/383 ,  G06F12/0848 ,  G06F2212/6028

    摘要： Disclosed is an instruction-level method and system for prefetching data or instructions of variable size to specified cache sets. A prefetch instruction containing binary fields allows the compiler, loader or runtime software to control cache prefetching and reduce thrashing by providing the prefetch hardware with information as to the optimal cache set location and the optimal amount of data to be prefetched. Support of Harvard architectures with separate instruction and data caches is provided by separate software control of instruction and data caches. The cache set number is identified to indicate into which set the information is to be preloaded. The size field provides a variable prefetch size. An address field indicates the address where prefetching begins.

    Hardware mechanism for optimizing instruction and data prefetching
    9.
    发明公开
    Hardware mechanism for optimizing instruction and data prefetching 失效
    五金 - Anordnung zur optimierten Vorausholung von Befehlen和Daten

    公开(公告)号：EP0810517A2

    公开(公告)日：1997-12-03

    申请号：EP97107455.4

    申请日：1997-05-06

    申请人： SUN MICROSYSTEMS, INC.

    发明人： Emberson, David R.

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F2212/6028

    摘要： Disclosed is a prefetch execution unit, prefetch instruction buffer and a prefetch victim buffer which operate to optimize prefetching by recording a particular cache miss' history. To record cache misses, victimized (overwritten) lines and/or a prefetch tag are stored in a prefetch victim buffer. When the processor experiences a cache miss, it accesses the prefetch victim buffer to retrieve information relating to the prefetch victim. The prefetch execution unit then modifies the values of the additional field or fields and then stores the modified augmented prefetch instruction in the prefetch instruction buffer. The next time a prefetch instruction for the victimized lines is executed by the processor, the new values of the modified augmented prefetch instruction will dictate where the prefetch information is stored or what size increment it has. By continuous modification of the augmented prefetch instructions, eventually thrashing may be eliminated.

    摘要翻译： 公开了一种预取执行单元，预取指令缓冲器和预取牺牲缓冲器，其通过记录特定高速缓存未命中历史来优化预取。 为了记录高速缓存未命中，受害（覆盖）行和/或预取标签存储在预取牺牲缓冲区中。 当处理器遇到缓存未命中时，它访问预取牺牲缓冲区以检索与预取受害者有关的信息。 然后，预取执行单元修改附加字段或值的值，然后将修改后的扩充预取指令存储在预取指令缓冲器中。 下一次由处理器执行受害线路的预取指令时，修改的增强预取指令的新值将指示预取信息存储在哪里或其具有的大小增量。 通过连续修改增强的预取指令，最终可能消除抖动。

    Memory management unit incorporating prefetch control
    10.
    发明公开
    Memory management unit incorporating prefetch control 失效
    Speicherverwaltungseinheit zur Vorauswahlsteuerung

    公开(公告)号：EP0752644A2

    公开(公告)日：1997-01-08

    申请号：EP96110735.6

    申请日：1996-07-03

    申请人： SUN MICROSYSTEMS, INC.

    发明人： Emberson, David R.

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/1027 ,  G06F2212/6028

    摘要： Disclosed is a method and system for providing for the prefetching of data or instructions A prefetch instruction which is in an instruction stream is processed by memory management unit (MMU) where prefetch cache control information is placed as part of the already existing prefetch instruction. Once processed by the MMU, the prefetch instruction thus contains binary fields allowing the operating system or runtime software to control cache prefetching by assigning values to the binary fields which provide the optimal cache set location and the optimal amount of data to be prefetched and thus reduces thrashing.

    摘要翻译： 公开了一种用于提供数据或指令的预取的方法和系统。指令流中的预取指令由存储器管理单元（MMU）处理，其中预取高速缓存控制信息被放置为已经存在的预取指令的一部分。 一旦由MMU处理，预取指令因此包含二进制字段，允许操作系统或运行时软件通过将值分配给二进制字段来控制高速缓存预取，这些二进制字段提供最佳高速缓存集位置和最佳数据量以便被预取，从而减少 颠簸。