公开(公告)号：EP1207445A3

公开(公告)日：2005-01-19

申请号：EP01126481.9

申请日：2001-11-09

申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

发明人： Bakker, Peter ,  Rennig, Fred

IPC分类号： G06F1/10

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03L7/06

摘要： The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time. This circuit component (62) is controlled in such a way as to change the signal transit time in inverse proportion to the changes of the output signals of the clock generator (16).

公开(公告)号：EP1207445A2

公开(公告)日：2002-05-22

申请号：EP01126481.9

申请日：2001-11-09

申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

发明人： Bakker, Peter ,  Rennig, Fred

IPC分类号： G06F1/10

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03L7/06

摘要： The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time. This circuit component (62) is controlled in such a way as to change the signal transit time in inverse proportion to the changes of the output signals of the clock generator (16).

摘要翻译： 用于产生与时钟发生器（16）的输出信号同步的半导体存储器（14）的时钟信号的电路配置包括输入级（20），时钟发生器（16）的输出信号 ）。 它还包含相位检测器（30），其接收由输入级（20）输出的信号，并且其输出信号控制提供半导体存储器（14）的时钟信号的压控振荡器（34）。 它还包含转换级（42），该转换级（42）将与振荡器（34）的输出信号有关的信号施加到相位检测器（30），该相位检测器（30）以这样的方式控制振荡器，使得从其到达的信号之间的相位差 输入级（20），并且也从转换级（42）到达的信号变为零。 输入级（20）包括一个放大器（44），该放大器（44）包含能够影响信号传输时间的电路部件（62）。 该电路部件（62）被控制成与时钟发生器（16）的输出信号的变化成反比地改变信号传播时间。

公开(公告)号：EP1176723B1

公开(公告)日：2003-10-08

申请号：EP01117740.9

申请日：2001-07-30

申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

发明人： Rennig, Fred S. ,  Bakker, Peter ,  Merk, Dieter

IPC分类号： H03K19/0185 ,  H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/018585

公开(公告)号：EP1176723A1

公开(公告)日：2002-01-30

申请号：EP01117740.9

申请日：2001-07-30

申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

发明人： Rennig, Fred S. ,  Bakker, Peter ,  Merk, Dieter

IPC分类号： H03K19/0185 ,  H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/018585

摘要： A driver circuit generates an adjustable output signal current at a driver output, which corresponds in each case to one or the other binary data level of an input signal. The driver circuit comprises n partial driver circuits (TT1-TT7), connected in parallel both at the input and at the output sides, which may be set into either an active or an inactive state for the purpose of setting the output signal current by means of a setting signal. In their active state each driver circuit delivers at each of its outputs a partial signal current relative to a constant reference current (Iref), depending on the data level of the input signal. The sum of the partial signal currents corresponds to the set output signal current. The input signals (INP, INN) are applied to a first partial driver circuit (TT1) directly, and to a second to nth partial driver circuit (TT2-TT7) via 1, 2, ... or n-1 delay elements (DP1-DP6, DN1-DN6) after a time delay of 1xΔt, 2xΔt up to (n-1)xΔt.

摘要翻译： 驱动器电路在驱动器输出处产生可调节的输出信号电流，其在每种情况下对应于输入信号的一个或另一个二进制数据电平。 驱动器电路包括在输入侧和输出侧并联连接的n个部分驱动电路（TT1-TT7），其可以被设置为有源或非活动状态，以便通过装置来设置输出信号电流 的设置信号。 在其工作状态下，每个驱动电路根据输入信号的数据电平，在每个输出端输出相对于恒定参考电流（Iref）的部分信号电流。 部分信号电流的和对应于设定的输出信号电流。 输入信号（INP，INN）被直接施加到第一部分驱动电路（TT1），并通过1,2或...或n-1延迟元件（第二部分驱动电路（TT2-TT7））施加到第二至第n部分驱动电路 DP1-DP6，DN1-DN6），在1x DELTA t，2x DELTA t到（n-1）×DELTA t的时间延迟之后。