-
公开(公告)号:EP3216053A4
公开(公告)日:2018-07-11
申请号:EP15857773
申请日:2015-11-06
IPC分类号: H01L23/485 , H01L21/50 , H01L23/13 , H01L23/14
CPC分类号: H01L23/147 , H01L21/481 , H01L21/4846 , H01L23/13 , H01L23/3738 , H01L24/83 , H01L24/97 , H01L2224/06181 , H01L2224/32225 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/15153 , H01L2924/157
摘要: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.