公开(公告)号：EP3376537A1

公开(公告)日：2018-09-19

申请号：EP16864377.3

申请日：2016-11-11

申请人： KYOCERA Corporation

发明人： FUKUOKA, Yasuhiko ,  YAMASAKO, Tadao ,  HIROOKA, Masashi

IPC分类号： H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L25/065 ,  H01L23/147 ,  H01L23/3142 ,  H01L24/48 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

摘要： An electronic component package 1 according to an embodiment of the present disclosure includes a first substrate 4, a sealing member 2, a second substrate 7, and connectors 16. The first substrate 4 has a first top surface 6 on which a first electronic component 3 is mounted. The sealing member 2 is positioned on the first top surface 6 and configured to seal the first electronic component 3 and a second electronic component 5. The second substrate 7 has a second top surface 10 on which the second electronic component 5 is mounted, and is positioned within the sealing member 2. The connectors 16 electrically couple the first substrate 4 and the second substrate 7.

公开(公告)号：EP3279938A4

公开(公告)日：2018-04-11

申请号：EP15887540

申请日：2015-03-30

申请人： PEZY COMPUTING K K

发明人： SAITO MOTOAKI

IPC分类号： H01L23/522 ,  H01L21/822 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/04 ,  H04B5/02

CPC分类号： H01L23/645 ,  H01F5/003 ,  H01F38/14 ,  H01L21/822 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/16 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L27/04 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H04B5/02

摘要： A semiconductor device equipped with a base board 10, a first element 20, a second element 30, and an interposer board 40, wherein: the first element 20 is positioned on the base board 10; a signal transmitting/receiving terminal 24 of the first element and a plurality of base board terminals 13 contact one another and are capable of transmitting and receiving a signal; the second element 30 is positioned on the base board 10; a signal transmitting/receiving terminal 34 of the second element and the plurality of base board terminals 13 contact one another and are capable of transmitting and receiving a signal; the interposer board 40 is positioned so as to extend on the first element 20 and the second element 30; a first contactless signal transmitting/receiving unit 43 of the interposer board is capable of contactlessly transmitting and receiving a signal to and from a contactless signal transmitting/receiving unit 25 of the first element via a first element board; and a second contactless signal transmitting/receiving unit 44 of the interposer board is capable of contactlessly transmitting and receiving a signal to and from a contactless signal transmitting/receiving unit 35 of the second element via a second element board 31.

公开(公告)号：EP2121511B1

公开(公告)日：2017-08-16

申请号：EP08705365.8

申请日：2008-01-25

申请人： Silex Microsystems AB

发明人： EBEFORS, Thorbjörn ,  KÄLVESTEN, Edvard ,  BAUER, Tomas

IPC分类号： B81B7/00 ,  B81C3/00 ,  H01L23/498 ,  H01L21/8234 ,  H01L21/762 ,  B81C1/00 ,  H01L23/26 ,  H01L23/14 ,  H01L23/055

CPC分类号： H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

摘要翻译： 半导体晶片（1）形式的起始衬底具有第一侧和第二侧，这些侧相对于彼此是平面平行的，并且具有使其适合于处理而没有显着受损的风险的厚度， 为了制造组合的模拟和数字设计，晶片包括至少两个通过完全延伸通过晶片延伸的绝缘材料（2; 38; 81; L）彼此电绝缘的分区（A1，A2; DIGITAL，ANALOGUE）。 还描述了用于制造这种衬底的方法，包括蚀刻晶片中的沟槽以及用绝缘材料填充沟槽。

公开(公告)号：EP3104410A4

公开(公告)日：2017-01-18

申请号：EP15762051

申请日：2015-01-28

申请人： MITSUBISHI HEAVY IND LTD

发明人： KATO MASAHIRO ,  KURODA YOSHIKATSU

IPC分类号： H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K1/18

CPC分类号： H01L25/0657 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/00

公开(公告)号：EP2380196B1

公开(公告)日：2016-06-08

申请号：EP10700172.9

申请日：2010-01-12

申请人： Epistar Corporation

发明人： SHIV, Lior ,  SHEPHERD, John, Nicholas

IPC分类号： H01L23/13 ,  H01L23/14 ,  H01L23/498

CPC分类号： H01L23/13 ,  B81B7/007 ,  B81B2207/096 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/48 ,  H01L33/486 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

公开(公告)号：EP2988325A3

公开(公告)日：2016-04-27

申请号：EP15181542.0

申请日：2015-08-19

申请人： General Electric Company

发明人： MCCONNELEE, Paul Alan ,  GOWDA, Arun Virupaksha

IPC分类号： H01L21/60 ,  H01L23/538 ,  H01L25/10

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

摘要： An electronics package includes a first dielectric substrate (34) having a first plurality of vias (50) formed through a thickness thereof, a metalized contact layer (48) coupled to a top surface (40) of the first dielectric substrate (34), and a first die (68) positioned within a first die opening (58) formed through the thickness of the first dielectric substrate (34). Metalized interconnects (56) are formed on a bottom surface (54) of the first dielectric substrate (34) and extend through the first plurality of vias (50) to contact the metalized contact layer (48). A second dielectric substrate (64) is coupled to the first dielectric substrate (34) and has a second plurality of vias (82) formed through a thickness thereof. Metalized interconnects (92) extend through the second plurality of vias (82) to contact the first plurality of metalized interconnects (56) and contact pads (49) of the first die (68). A first conductive element electrically (114) couples the first die (68) to the metalized contact layer (48).

摘要翻译： 一种电子器件封装包括：具有穿过其厚度形成的第一多个通孔（50）的第一电介质衬底（34）;耦合到第一电介质衬底（34）的顶表面（40）的金属化接触层（48） 和定位在穿过第一电介质衬底（34）的厚度形成的第一模具开口（58）内的第一管芯（68）。 金属互连（56）形成在第一电介质衬底（34）的底表面（54）上并延伸穿过第一多个通孔（50）以接触金属化接触层（48）。 第二电介质基片（64）连接到第一电介质基片（34），并具有穿过其厚度形成的第二多个通孔（82）。 金属化互连（92）延伸穿过第二多个通孔（82）以接触第一管芯（68）的第一多个金属化互连（56）和接触垫（49）。 第一导电元件电（114）将第一管芯（68）耦合到金属化接触层（48）。

公开(公告)号：EP2988325A2

公开(公告)日：2016-02-24

申请号：EP15181542.0

申请日：2015-08-19

申请人： General Electric Company

发明人： MCCONNELEE, Paul Alan ,  GOWDA, Arun Virupaksha

IPC分类号： H01L21/60 ,  H01L23/538 ,  H01L25/10

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

摘要： An electronics package includes a first dielectric substrate (34) having a first plurality of vias (50) formed through a thickness thereof, a metalized contact layer (48) coupled to a top surface (40) of the first dielectric substrate (34), and a first die (68) positioned within a first die opening (58) formed through the thickness of the first dielectric substrate (34). Metalized interconnects (56) are formed on a bottom surface (54) of the first dielectric substrate (34) and extend through the first plurality of vias (50) to contact the metalized contact layer (48). A second dielectric substrate (64) is coupled to the first dielectric substrate (34) and has a second plurality of vias (82) formed through a thickness thereof. Metalized interconnects (92) extend through the second plurality of vias (82) to contact the first plurality of metalized interconnects (56) and contact pads (49) of the first die (68). A first conductive element electrically (114) couples the first die (68) to the metalized contact layer (48).

摘要翻译： 在电子封装衬底包括通过厚度形成的第一电介质（34）具有通孔的第一多个（50）其耦合到所述第一电介质基片的顶部表面（40）的金属化接触层（48）（34） 以及第一至（68）的开口部内定位在第一（58）穿过所述第一电介质基片（34）的厚度形成。 金属化互连件（56）形成在所述第一电介质基片（34）的底表面（54）和通孔（50）的所述第一多个延伸以接触金属化接触层（48）。 一第二介电基片（64）被耦合到所述第一电介质基片（34）和具有穿过其厚度形成的通孔（82）的第二多个。 金属化互连件（92）通孔（82）的所述第二多个延伸到第一金属化的互连（56）和接触垫（49）的所述第一多个接触到（68）。 的第一导电元件电（114）耦合所述第一对（68），以金属化接触层（48）。

公开(公告)号：EP2966680A1

公开(公告)日：2016-01-13

申请号：EP13877188.6

申请日：2013-03-07

申请人： TOHOKU-MICROTEC CO., LTD

发明人： MOTOYOSHI, Makoto

IPC分类号： H01L25/065 ,  H01L21/60 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L24/14 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/09517 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1134 ,  H01L2224/11444 ,  H01L2224/1147 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/8109 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01322 ,  H01L2924/15192 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2924/01013 ,  H01L2924/01032 ,  H01L2924/01051 ,  H01L2924/0105 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81

摘要： A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

摘要翻译： 堆叠器件包括下部芯片，该下部芯片包括多个布线连接盘和多个壁挂块图案，每个壁块图案被分配在除布置连线连接盘的位置之外的位置处，每个壁块图案 具有倾斜平面，从布线连接盘的阵列的参考平面测量的每个壁块图案的高度高于布线连接盘，并且包括多个布线凸点的上部芯片对应于 布线焊盘以及分别对应于壁块图案的位置分配的多个锥形凸块。

公开(公告)号：EP2826066A4

公开(公告)日：2015-12-16

申请号：EP13760504

申请日：2013-03-12

申请人： SILEX MICROSYSTEMS AB

发明人： EBEFORS THORBJÖRN ,  PERTTU DANIEL

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/525

CPC分类号： H01L23/49827 ,  H01L21/30625 ,  H01L21/308 ,  H01L21/486 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/525 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/05552

摘要： The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.

公开(公告)号：EP2859582A2

公开(公告)日：2015-04-15

申请号：EP13783123.6

申请日：2013-06-06

申请人： Invensas Corporation

发明人： UZOH, Cyprian Emeka ,  WOYCHIK, Charles G. ,  CASKEY, Terrence ,  DESAI, Kishor V. ,  WEI, Huailiang ,  MITCHELL, Craig ,  HABA, Belgacem

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/34 ,  H01L21/76841 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/32105 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81805

摘要： A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.