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公开(公告)号：EP1249944A3
公开(公告)日：2005-12-21
申请号：EP02100354.6
申请日：2002-04-08
IPC分类号： H04B1/28
CPC分类号： H04B1/0025 , H04B1/0003 , H04B1/28 , H04B1/30
摘要： A subsampling receiver (50, 50', 50") for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50', 50") may be implemented into a wireless communications device (40), such as a wireless telephone handset. In one disclosed embodiment, the receiver (50) includes a sample and hold circuit (80) that samples a bandpass filtered input modulated signal at the subsampling frequency (f s ) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (85I, 85Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver (50') includes two sample and hold circuits (96I, 96Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components. In a third embodiment, the receiver (50") includes an analog mixer (116) to downconvert the RF input to an intermediate frequency, prior to digitization and digital mixing at quadrature phase.
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2.发明公开Method for tuning a voltage controlled oscillator 有权维尔法罕zur Abstimmung eines spannungsgesteuerten Oszillators
公开(公告)号：EP1189351A2
公开(公告)日：2002-03-20
申请号：EP01000388.7
申请日：2001-08-17
摘要： A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO nonlinearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.
摘要翻译： 具有混合数字粗略VCO调谐和VCO温度漂移补偿的非常快速的锁定整数N PLL提供了完全数字调谐方案，而不需要电荷泵。 使用这种PLL设计的PLL合成器（300）通过使用开环步骤和闭环步骤提供非常快的锁定时间。 混合PLL可以在四个时钟周期内实现粗调谐，同时最小化由VCO非线性引起的任何误差。 还提供温度跟踪和补偿。 还描述了SAR实现（100）和插值调谐实现（200）。
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公开(公告)号：EP1249944B1
公开(公告)日：2014-07-16
申请号：EP02100354.6
申请日：2002-04-08
CPC分类号： H04B1/0025 , H04B1/0003 , H04B1/28 , H04B1/30
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公开(公告)号：EP1249944A2
公开(公告)日：2002-10-16
申请号：EP02100354.6
申请日：2002-04-08
IPC分类号： H04B1/28
CPC分类号： H04B1/0025 , H04B1/0003 , H04B1/28 , H04B1/30
摘要： A subsampling receiver (50, 50', 50") for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50', 50") may be implemented into a wireless communications device (40), such as a wireless telephone handset. In one disclosed embodiment, the receiver (50) includes a sample and hold circuit (80) that samples a bandpass filtered input modulated signal at the subsampling frequency (f s ) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (85I, 85Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver (50') includes two sample and hold circuits (96I, 96Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components. In a third embodiment, the receiver (50") includes an analog mixer (116) to downconvert the RF input to an intermediate frequency, prior to digitization and digital mixing at quadrature phase.
摘要翻译： 带通滤波器（70,74,78）对包括由有效载荷信号调制的RF载波信号的输入信号进行滤波。 采样和保持电路（80）以低于RF载波频率但是有效载荷信号的带宽的两倍的频率对经滤波的信号进行采样。 A / D转换器（84）以基带频率数字化采样信号并对应于有效载荷信号。 包括以下独立权利要求：（1）无线通信单元; 和（2）调制信号转换方法。
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公开(公告)号：EP1189351B1
公开(公告)日：2006-10-25
申请号：EP01000388.7
申请日：2001-08-17
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公开(公告)号：EP1189351A3
公开(公告)日：2002-08-07
申请号：EP01000388.7
申请日：2001-08-17
摘要： A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO nonlinearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.
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