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    OSCILLATOR CALIBRATION FROM OVER-THE AIR SIGNALS
    1.
    发明公开
    OSCILLATOR CALIBRATION FROM OVER-THE AIR SIGNALS 审中-实审

    公开(公告)号：EP4366172A2

    公开(公告)日：2024-05-08

    申请号：EP24164297.4

    申请日：2019-03-20

    申请人： Wiliot, Ltd.

    发明人： Yehezkely, Alon

    IPC分类号： H03L7/181

    CPC分类号： H03J2200/1120130101 ,  H03L7/181 ,  H03L2207/0620130101 ,  H03L7/23 ,  H03L7/099

    摘要： Oscillator calibration circuits and wireless transmitters including oscillator calibration circuits. An oscillator calibration circuit includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session.

    Clock signal generation apparatus
    4.
    发明公开
    Clock signal generation apparatus 审中-公开
    装置，用于产生一个时钟信号

    公开(公告)号：EP0914010A3

    公开(公告)日：2004-08-25

    申请号：EP98120402.7

    申请日：1998-10-28

    申请人： Victor Company of Japan, Ltd.

    发明人： Ohishi, Takeo

    IPC分类号： H04N7/62 ,  H03L7/14

    CPC分类号： H04N21/6336 ,  H03L7/095 ,  H03L7/146 ,  H03L7/181 ,  H04N21/4135 ,  H04N21/4305 ,  H04N21/6112

    摘要： A clock signal generation apparatus includes a first device for extracting reference information from an input digital signal. An oscillator operates for generating a reference clock signal having a frequency depending on a control signal. A second device connected to the first device and the oscillator operates for generating the control signal to the oscillator in response to the reference clock signal generated by the oscillator and the reference information extracted by the first device, and for locking a phase of the reference clock signal to the reference information. A third device connected to the second device operates for deciding whether or not the phase of the reference clock signal is successfully locked to the reference information. A fourth device connected to the second device, a memory, and the third device operates for storing the control signal generated by the second device into the memory when the third device decides that the phase of the reference clock signal is successfully locked to the reference information. A fifth device connected to the memory, the oscillator, and the second device operates for selecting one of the control signal currently generated by the second device and the control signal stored in the memory, and for feeding the selected control signal to the oscillator.

    Phasenregelkreis mit geringem Phasenfehler
    7.
    发明公开
    Phasenregelkreis mit geringem Phasenfehler 审中-公开

    公开(公告)号：EP1032133A1

    公开(公告)日：2000-08-30

    申请号：EP00102996.6

    申请日：2000-02-14

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Trimmel, Herwig ,  Thanhäuser, Gerhard ,  Stummer, Baldur

    IPC分类号： H03L7/08

    CPC分类号： H03L7/091 ,  H03L7/085 ,  H03L7/181

    摘要： Ein Phasenregelkreis zur Regelung der Phase eines Ausgangssignals S2 in Abhängigkeit von einem Referenzsignal S1 mit geringem Phasenzeitfehler weist eine Abtastschaltung (2; 13) zur Abtastung des Referenzsignals S1 durch das Ausgangssignal S2 und zur Erzeugung eines Abtastsignals S1A, eine Jitter-Modulationsschaltung (3) zur Erzeugung eines um eine festgelegte Zeitdauer verzögerten Abtastsignals S1AJ und zur abwechselnden Ausgabe des unverzögerten Abtastsignals S1A und des verzögerten Abtastsignals S1AJ, einen Phasendetektor (6) zur Erfassung einer mittleren Phasendifferenz zwischen dem Ausgangssignal S2 und den verzögerten und unverzögerten Abtastsignalen S1A und S1AJ und einen regelbaren Oszillator (11) zur Erzeugung des Ausgangssignals S2 mit einer in Abhängigkeit von der durch den Phasendetektor (6) erfaßten mittleren Phasendifferenz regelbaren Frequenz auf.

    摘要翻译： 用于相对于参考信号（S1）控制输出信号（S2）相位的锁相环电路包括：采样电路（2），用于通过输出信号对参考信号（S1）进行采样，并产生采样信号（S1A ）。 抖动调制电路（3）提供具有固定时间延迟的采样信号（S1AJ），用于未延迟采样信号（S1A）和延迟采样信号（S1AJ）的交替输出。 相位检测器（6）确定输出信号（S2）和延迟和未延迟采样信号（S1A）和（S1AJ）之间的平均相位差，压控振荡器（VCO）（11）产生输出信号 （S2）具有取决于由相位检测器（6）检测的平均相位差的受控频率。

    Reference clock generation circuit
    8.
    发明公开
    Reference clock generation circuit 失效
    基准时钟发生器电路

    公开(公告)号：EP0700045A2

    公开(公告)日：1996-03-06

    申请号：EP95113606.8

    申请日：1995-08-30

    申请人： AIWA CO., LTD.

    发明人： Watanabe, Hiroyuki ,  Takarada, Satoshi

    IPC分类号： G11B20/14

    CPC分类号： G11B27/3027 ,  G11B20/1403 ,  H03L7/085 ,  H03L7/181 ,  H04L7/042

    摘要： A pulse interval time measurement block receives a synchronizing signal, and a reference clock signal, which reference clock signal is provided from a resistance value control oscillator, and counts the pulse time interval in the synchronizing signal in accordance with the reference clock signal. The count data is latched and supplied to a converter, which generates a resistance value based on the count data. The frequency of the reference clock signal is set to be equal to that of the synchronizing signal multiplied by the predetermined number, based on the resistance value. The latched data is stored until it is updated by the data of the next synchronizing signal. Even when the synchronizing signal is supplied over a short period of time or its cycle is changed, the pulse interval is automatically measured, and it is possible for the frequency of the reference clock signal to be set to be equal to that of the synchronizing signal multiplied by the predetermined number.

    Frequency synthesizing circuit
    9.
    发明公开
    Frequency synthesizing circuit 失效
    频率合成电路。

    公开(公告)号：EP0083823A1

    公开(公告)日：1983-07-20

    申请号：EP82201671.3

    申请日：1982-12-29

    申请人： Philips Electronics N.V.

    发明人： Geurts, Martinus F. A. M.

    IPC分类号： H03L7/18 ,  H03J7/06 ,  G01R23/10

    CPC分类号： H03J7/06 ,  G01R23/10 ,  H03L7/181

    摘要： in a frequency synthesizing circuit the deviation of the frequency of an oscillator signal which is transmitted (at 7) by a measuring gate (79) from a desired frequency (output 47) is converted into a control signal (at 3) for the oscillator (11). In order to prevent the occurrence of an average frequency-deviation due to a continuous change of the phase relationship between a test pulse (m) controlling the measuring gate (79) and the oscillator signal, an additional pulse (output 83 or 85) is added (via 81) to the output signal of the measuring gate (79). This additional pulse must occur contiguous to the test pulse.