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公开(公告)号：EP0157607A3
公开(公告)日：1988-01-20
申请号：EP85302197
申请日：1985-03-29
发明人： Walker, James Terrell , Larsen, Raymond Sverre , Shapiro, Stephen Loeb , Chae, Soo Ik , Freytag, Dietrich Reinhold , Breidenbach, Martin
IPC分类号： G11C27/02
CPC分类号： G11C27/04 , G11C27/026
摘要： A high speed data storage array is disclosed utilizing a cell design allowing high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates (Q1, Q2) between the signal input and a storage capacitor (20). The gates are controlled by a high speed row clock (12) and low speed column clock (28) the instantaneous analog value of the signal being sampled and stored by a cell on coincidence of the two clocks.
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公开(公告)号：EP0157607A2
公开(公告)日：1985-10-09
申请号：EP85302197.0
申请日：1985-03-29
发明人： Walker, James Terrell , Larsen, Raymond Sverre , Shapiro, Stephen Loeb , Chae, Soo Ik , Freytag, Dietrich Reinhold , Breidenbach, Martin
IPC分类号： G11C27/02
CPC分类号： G11C27/04 , G11C27/026
摘要： A high speed data storage array is disclosed utilizing a cell design allowing high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates (Q1, Q2) between the signal input and a storage capacitor (20). The gates are controlled by a high speed row clock (12) and low speed column clock (28) the instantaneous analog value of the signal being sampled and stored by a cell on coincidence of the two clocks.
摘要翻译： 利用允许快速变化的信号的高速采样的单元设计来公开高速数据存储阵列。 阵列的每个单元包括在信号输入端和存储电容器（20）之间的两个输入门（Q1，Q2）。 栅极由高速行时钟（12）和低速列时钟（28）控制，信号的瞬时模拟值由两个时钟的一致性由单元采样和存储。
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公开(公告)号：EP0157607B1
公开(公告)日：1993-02-10
申请号：EP85302197.0
申请日：1985-03-29
发明人： Walker, James Terrell , Larsen, Raymond Sverre , Shapiro, Stephen Loeb , Chae, Soo Ik , Freytag, Dietrich Reinhold , Breidenbach, Martin
IPC分类号： G11C27/02
CPC分类号： G11C27/04 , G11C27/026
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